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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id jh2-20020a170903328200b001bc35b14c99sm802768plb.212.2023.09.07.23.43.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Sep 2023 23:43:09 -0700 (PDT) Received: from hqs-appsw-appswa2.mp600.macronix.com (linux-patcher [172.17.236.35]) by twhmp6px (Postfix) with ESMTPS id DD33780E2B; Fri, 8 Sep 2023 14:45:06 +0800 (CST) From: Jaime Liao To: linux-mtd@lists.infradead.org, tudor.ambarus@linaro.org, pratyush@kernel.org, michael@walle.cc, miquel.raynal@bootlin.com Cc: leoyu@mxic.com.tw, jaimeliao@mxic.com.tw Subject: [PATCH v4 1/6] mtd: spi-nor: Add manufacturer read id function Date: Fri, 8 Sep 2023 14:42:59 +0800 Message-Id: <20230908064304.27757-2-jaimeliao.tw@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908064304.27757-1-jaimeliao.tw@gmail.com> References: <20230908064304.27757-1-jaimeliao.tw@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230907_234312_405458_B92A0350 X-CRM114-Status: GOOD ( 19.40 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: JaimeLiao Add manufacturer read id function because of some flash may change data format when read id in octal dtr mode. Signed-off-by: JaimeLiao --- drivers/mtd/spi-nor/core.c | 30 ++++++++++++++++++++++++++++-- drivers/mtd/spi-nor/core.h | 6 ++++++ drivers/mtd/spi-nor/macronix.c | 18 ++++++++++++++++++ 3 files chang [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:531 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [jaimeliao.tw[at]gmail.com] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: JaimeLiao Add manufacturer read id function because of some flash may change data format when read id in octal dtr mode. Signed-off-by: JaimeLiao --- drivers/mtd/spi-nor/core.c | 30 ++++++++++++++++++++++++++++-- drivers/mtd/spi-nor/core.h | 6 ++++++ drivers/mtd/spi-nor/macronix.c | 18 ++++++++++++++++++ 3 files changed, 52 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 1b0c6770c14e..7ee624b16e17 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -408,7 +408,7 @@ int spi_nor_write_disable(struct spi_nor *nor) } /** - * spi_nor_read_id() - Read the JEDEC ID. + * spi_nor_default_read_id() - Read the JEDEC ID. * @nor: pointer to 'struct spi_nor'. * @naddr: number of address bytes to send. Can be zero if the operation * does not need to send an address. @@ -420,7 +420,7 @@ int spi_nor_write_disable(struct spi_nor *nor) * * Return: 0 on success, -errno otherwise. */ -int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, +int spi_nor_default_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, enum spi_nor_protocol proto) { int ret; @@ -438,6 +438,32 @@ int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, return ret; } +/** + * spi_nor_read_id() - Read ID by manufacturer read id function. + * @nor: pointer to 'struct spi_nor'. + * @naddr: number of address bytes to send. Can be zero if the operation + * does not need to send an address. + * @ndummy: number of dummy bytes to send after an opcode or address. Can + * be zero if the operation does not require dummy bytes. + * @id: pointer to a DMA-able buffer where the value of the JEDEC ID + * will be written. + * @proto: the SPI protocol for register operation. + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, + enum spi_nor_protocol proto) +{ + int ret; + + if (nor->manufacturer && nor->manufacturer->fixups && nor->manufacturer->fixups->read_id) + ret = nor->manufacturer->fixups->read_id(nor, naddr, ndummy, id, proto); + else + ret = spi_nor_default_read_id(nor, naddr, ndummy, id, proto); + + return ret; +} + /** * spi_nor_read_sr() - Read the Status Register. * @nor: pointer to 'struct spi_nor'. diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 9217379b9cfe..92cbc2d3f7fe 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -424,6 +424,8 @@ struct spi_nor_flash_parameter { * @late_init: used to initialize flash parameters that are not declared in the * JESD216 SFDP standard, or where SFDP tables not defined at all. * Will replace the default_init() hook. + * @read_id: used to read id which may change format after enter into + octal dtr mode. * * Those hooks can be used to tweak the SPI NOR configuration when the SFDP * table is broken or not available. @@ -435,6 +437,8 @@ struct spi_nor_fixups { const struct sfdp_bfpt *bfpt); int (*post_sfdp)(struct spi_nor *nor); int (*late_init)(struct spi_nor *nor); + int (*read_id)(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, + enum spi_nor_protocol reg_proto); }; /** @@ -667,6 +671,8 @@ void spi_nor_unlock_and_unprep(struct spi_nor *nor); int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor); int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor); int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor); +int spi_nor_default_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, + enum spi_nor_protocol reg_proto); int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, enum spi_nor_protocol reg_proto); int spi_nor_read_sr(struct spi_nor *nor, u8 *sr); diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index eb149e517c1f..8ab47691dfbb 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -118,9 +118,27 @@ static int macronix_nor_late_init(struct spi_nor *nor) return 0; } +static int macronix_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, + enum spi_nor_protocol proto) +{ + int i, ret; + + ret = spi_nor_default_read_id(nor, naddr, ndummy, id, proto); + /* Retrieve odd array and re-sort id because of read id format will be A-A-B-B-C-C + * after enter into octal dtr mode for Macronix flashes. + */ + if (proto == SNOR_PROTO_8_8_8_DTR) { + for (i = 0; i < nor->info->id_len; i++) + id[i] = id[i*2]; + } + + return ret; +} + static const struct spi_nor_fixups macronix_nor_fixups = { .default_init = macronix_nor_default_init, .late_init = macronix_nor_late_init, + .read_id = macronix_nor_read_id, }; const struct spi_nor_manufacturer spi_nor_macronix = { From patchwork Fri Sep 8 06:43:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liao jaime X-Patchwork-Id: 1831314 X-Patchwork-Delegate: tudor.ambarus@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=E8tHJR5o; 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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id d2-20020aa78142000000b00666b012baedsm671944pfn.158.2023.09.07.23.43.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Sep 2023 23:43:10 -0700 (PDT) Received: from hqs-appsw-appswa2.mp600.macronix.com (linux-patcher [172.17.236.35]) by twhmp6px (Postfix) with ESMTPS id 7F85780E44; Fri, 8 Sep 2023 14:45:07 +0800 (CST) From: Jaime Liao To: linux-mtd@lists.infradead.org, tudor.ambarus@linaro.org, pratyush@kernel.org, michael@walle.cc, miquel.raynal@bootlin.com Cc: leoyu@mxic.com.tw, jaimeliao@mxic.com.tw Subject: [PATCH v4 2/6] mtd: spi-nor: add Octal DTR support for Macronix flash Date: Fri, 8 Sep 2023 14:43:00 +0800 Message-Id: <20230908064304.27757-3-jaimeliao.tw@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908064304.27757-1-jaimeliao.tw@gmail.com> References: <20230908064304.27757-1-jaimeliao.tw@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230907_234313_095981_CC4AD037 X-CRM114-Status: GOOD ( 18.00 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: JaimeLiao Create Macronix specify method for enable Octal DTR mode and set 20 dummy cycles to allow running at the maximum supported frequency for Macronix Octal flash. Use number of dummy cycles which is parse by SFDP then convert it to bit pattern and set in CR2 register. Set CR2 register for enable octal dtr mode. Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:22f listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [jaimeliao.tw[at]gmail.com] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: JaimeLiao Create Macronix specify method for enable Octal DTR mode and set 20 dummy cycles to allow running at the maximum supported frequency for Macronix Octal flash. Use number of dummy cycles which is parse by SFDP then convert it to bit pattern and set in CR2 register. Set CR2 register for enable octal dtr mode. Signed-off-by: JaimeLiao Co-developed-by: Tudor Ambarus --- drivers/mtd/spi-nor/macronix.c | 97 ++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index 8ab47691dfbb..28c49c98503a 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -8,6 +8,24 @@ #include "core.h" +#define SPINOR_OP_MXIC_RD_ANY_REG 0x71 /* Read volatile configuration register 2 */ +#define SPINOR_OP_MXIC_WR_ANY_REG 0x72 /* Write volatile configuration register 2 */ +#define SPINOR_REG_MXIC_CR2_MODE 0x00000000 /* CR2 address for setting octal DTR mode */ +#define SPINOR_REG_MXIC_CR2_DC 0x00000300 /* CR2 address for setting dummy cycles */ +#define SPINOR_REG_MXIC_OPI_DTR_EN 0x2 /* Enable Octal DTR */ +#define SPINOR_REG_MXIC_SPI_EN 0x0 /* Enable SPI */ +#define SPINOR_REG_MXIC_ADDR_BYTES 4 /* Fixed R/W volatile address bytes to 4 */ +/* Convert dummy cycles to bit pattern */ +#define SPINOR_REG_MXIC_DC(p) \ + ((20 - p)/2) + +/* Macronix SPI NOR flash operations. */ +#define MXIC_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MXIC_WR_ANY_REG, 0), \ + SPI_MEM_OP_ADDR(naddr, addr, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) + static int mx25l25635_post_bfpt_fixups(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, @@ -105,6 +123,84 @@ static const struct flash_info macronix_nor_parts[] = { FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, }; +static int macronix_nor_octal_dtr_en(struct spi_nor *nor) +{ + struct spi_mem_op op; + u8 *buf = nor->bouncebuf; + int ret; + + /* Use dummy cycles which is parse by SFDP and convert to bit pattern. */ + buf[0] = SPINOR_REG_MXIC_DC(nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].num_wait_states); + op = (struct spi_mem_op) + MXIC_NOR_WR_ANY_REG_OP(SPINOR_REG_MXIC_ADDR_BYTES, + SPINOR_REG_MXIC_CR2_DC, 1, buf); + + ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + + /* Set the octal and DTR enable bits. */ + buf[0] = SPINOR_REG_MXIC_OPI_DTR_EN; + op = (struct spi_mem_op) + MXIC_NOR_WR_ANY_REG_OP(SPINOR_REG_MXIC_ADDR_BYTES, + SPINOR_REG_MXIC_CR2_MODE, 1, buf); + ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + + /* Read flash ID to make sure the switch was successful. */ + ret = spi_nor_read_id(nor, 4, 4, buf, SNOR_PROTO_8_8_8_DTR); + if (ret) { + dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret); + return ret; + } + + if (memcmp(buf, nor->info->id, nor->info->id_len)) + return -EINVAL; + + return 0; +} + +static int macronix_nor_octal_dtr_dis(struct spi_nor *nor) +{ + struct spi_mem_op op; + u8 *buf = nor->bouncebuf; + int ret; + + /* + * The register is 1-byte wide, but 1-byte transactions are not + * allowed in 8D-8D-8D mode. Since there is no register at the + * next location, just initialize the value to 0 and let the + * transaction go on. + */ + buf[0] = SPINOR_REG_MXIC_SPI_EN; + buf[1] = 0x0; + op = (struct spi_mem_op) + MXIC_NOR_WR_ANY_REG_OP(SPINOR_REG_MXIC_ADDR_BYTES, + SPINOR_REG_MXIC_CR2_MODE, 2, buf); + ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); + if (ret) + return ret; + + /* Read flash ID to make sure the switch was successful. */ + ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); + if (ret) { + dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret); + return ret; + } + + if (memcmp(buf, nor->info->id, nor->info->id_len)) + return -EINVAL; + + return 0; +} + +static int macronix_nor_set_octal_dtr(struct spi_nor *nor, bool enable) +{ + return enable ? macronix_nor_octal_dtr_en(nor) : + macronix_nor_octal_dtr_dis(nor); +} + static void macronix_nor_default_init(struct spi_nor *nor) { nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable; @@ -114,6 +210,7 @@ static int macronix_nor_late_init(struct spi_nor *nor) { if (!nor->params->set_4byte_addr_mode) nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_en4b_ex4b; + nor->params->set_octal_dtr = macronix_nor_set_octal_dtr; return 0; } From patchwork Fri Sep 8 06:43:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liao jaime X-Patchwork-Id: 1831316 X-Patchwork-Delegate: tudor.ambarus@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=GBDzX1qz; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20221208 header.b=o9rt4hGi; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; 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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id t20-20020aa79394000000b0064d47cd116esm678627pfe.161.2023.09.07.23.43.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Sep 2023 23:43:11 -0700 (PDT) Received: from hqs-appsw-appswa2.mp600.macronix.com (linux-patcher [172.17.236.35]) by twhmp6px (Postfix) with ESMTPS id 0E46480E5C; Fri, 8 Sep 2023 14:45:08 +0800 (CST) From: Jaime Liao To: linux-mtd@lists.infradead.org, tudor.ambarus@linaro.org, pratyush@kernel.org, michael@walle.cc, miquel.raynal@bootlin.com Cc: leoyu@mxic.com.tw, jaimeliao@mxic.com.tw Subject: [PATCH v4 3/6] mtd: spi-nor: add support for Macronix Octal flash Date: Fri, 8 Sep 2023 14:43:01 +0800 Message-Id: <20230908064304.27757-4-jaimeliao.tw@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908064304.27757-1-jaimeliao.tw@gmail.com> References: <20230908064304.27757-1-jaimeliao.tw@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230907_234315_153064_6B96D8BE X-CRM114-Status: UNSURE ( 5.96 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: JaimeLiao Adding Macronix Octal flash for Octal DTR support. The octaflash series can be divided into the following types: Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:32d listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [jaimeliao.tw[at]gmail.com] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: JaimeLiao Adding Macronix Octal flash for Octal DTR support. The octaflash series can be divided into the following types: MX25 series : Serial NOR Flash. MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb) LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation. LW/UW series : Support simultaneous Read-while-Write operation in multiple bank architecture. Read-while-write feature which means read data one bank while another bank is programing or erasing. MX25LM : 3.0V Octal I/O -https://www.mxic.com.tw/Lists/Datasheet/Attachments/8729/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf MX25UM : 1.8V Octal I/O -https://www.mxic.com.tw/Lists/Datasheet/Attachments/8967/MX25UM51245G,%201.8V,%20512Mb,%20v1.5.pdf MX66LM : 3.0V Octal I/O with stacked die -https://www.mxic.com.tw/Lists/Datasheet/Attachments/8748/MX66LM1G45G,%203V,%201Gb,%20v1.1.pdf MX66UM : 1.8V Octal I/O with stacked die -https://www.mxic.com.tw/Lists/Datasheet/Attachments/8711/MX66UM1G45G,%201.8V,%201Gb,%20v1.1.pdf MX25LW : 3.0V Octal I/O with Read-while-Write MX25UW : 1.8V Octal I/O with Read-while-Write MX66LW : 3.0V Octal I/O with Read-while-Write and stack die MX66UW : 1.8V Octal I/O with Read-while-Write and stack die About LW/UW series, please contact us freely if you have any questions. For adding Octal NOR Flash IDs, we have validated each Flash on plateform zynq-picozed. As below are the SFDP table dump. zynq> cat jedec_id c2943c zynq> cat manufacturer macronix zynq> cat partname mx66uw2g345gx0 zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff0000000000000000ffffffff ffffffffe5208affffffff7f00ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff87790100841200e2cc04674630b030b0f4bdd55c 000000ff101000200000000000007c234800000000008888000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 000a00001445988043061f0021dcffff zynq> md5sum sfdp 839ad44d1e758bea30bd9917ba763ba6 sfdp zynq> cat jedec_id c2853b zynq> cat manufacturer macronix zynq> cat partname mx66lm1g45g zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff0000000000000000ffffffff ffffffffe5208affffffff3f00ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff87690100821200e2cc02673830b030b0f4bdd55c 000000ff101000200000000000007ca34800000000006666000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 0000000014351c0043060f0021dcffff zynq> md5sum sfdp 7b46113b529d58a6335531a10f14a76e sfdp zynq> cat jedec_id c2853a zynq> cat manufacturer macronix zynq> cat partname mx25lm51245g zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff0000000000000000ffffffff ffffffffe5208affffffff1f00ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff897901008d1200e2cc02674430b030b0f4bdd55c 000000ff101000200000000000007ca34800000000006666000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 0000000014351c0043060f0021dcffff zynq> md5sum sfdp 214868617d74e6bfb2c45444d5d6fff0 sfdp zynq> cat jedec_id c2863a zynq> cat manufacturer macronix zynq> cat partname mx25lw51245g zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff000000000000000000000000 00000000e5208affffffff1f00ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff8b7901008f1200e2cc04674630b030b0f4bdd55c 000000ff101000200000000000007ca34800000000006666000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 0000000014351c0043060f0021dcffff zynq> md5sum sfdp bb32ccaca6814f3104b985ac91bd65ac sfdp zynq> cat jedec_id c28539 zynq> cat manufacturer macronix zynq> cat partname mx25lm25645g zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff0000000000000000ffffffff ffffffffe5208affffffff0f00ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff87690100821200d2cc02673830b030b0f4bdd55c 000000ff101000200000000000007ca34800000000006666000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 0000000014351c0043060f0021dcffff zynq> md5sum sfdp ec258f831ac737454c7eb9f6a8a4495a sfdp zynq> cat jedec_id c2843c zynq> cat manufacturer macronix zynq> cat partname mx66uw2g345g zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff0000000000000000ffffffff ffffffffe5208affffffff7f00ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff87790100841200e2cc04674630b030b0f4bdd55c 000000ff101000200000147c00007c234800000000007777000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 000000001445988043061f0021dcffff zynq> md5sum sfdp 00447475e039e67c256a8d75d5885ae8 sfdp zynq> cat jedec_id c2803b zynq> cat manufacturer macronix zynq> cat partname mx66um1g45g zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff0000000000000000ffffffff ffffffffe5208affffffff3f00ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff897901008d1200e2cc02674430b030b0f4bdd55c 000000ff101000200000000000007ca34800000000008888000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 000a000014359c8043060f0021dcffff zynq> md5sum sfdp eea09d64679e64f627402b39a177e356 sfdp zynq> cat jedec_id c2813b zynq> cat manufacturer macronix zynq> cat partname mx66uw1g45g zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff0000000000000000ffffffff ffffffffe5208affffffff3f00ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff8b7901008f1200e2cc04674630b030b0f4bdd55c 000000ff101000200000000000007ca34800000000008888000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 000a00001445988043060f0021dcffff zynq> md5sum sfdp b89a53266007fce06ba7cc4c0956f917 sfdp zynq> cat jedec_id c2843a zynq> cat manufacturer macronix zynq> cat partname mx25uw51345g zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff0000000000000000ffffffff ffffffffe5208affffffff1f00ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff8b7901008f1200e2cc04674630b030b0f4bdd55c 000000ff101000200000000000007c234800000000008888000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 000a00001445988043060f0021dcffff zynq> md5sum sfdp cdccbfad3c384e77f3a5f7847b57b148 sfdp zynq> cat jedec_id c28039 zynq> cat manufacturer macronix zynq> cat partname mx25um25645g zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff0000000000000000ffffffff ffffffffe5208affffffff0f00ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff87790100841200d2cc02673830b030b0f4bdd55c 000000ff101000200000000000007ca34800000000008888000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 000a000014359c8043060f0021dcffff zynq> md5sum sfdp d652779f17770dc833cd96262cb2a620 sfdp zynq> cat jedec_id c28139 zynq> cat manufacturer macronix zynq> cat partname mx25uw25645g zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff0000000000000000ffffffff ffffffffe5208affffffff0f00ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff897901008d1200d2cc04674630b030b0f4bdd55c 000000ff101000200000000000007ca34800000000008888000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 000a00001445988043060f0021dcffff zynq> md5sum sfdp e43ab2dbcbcf99cebc74964c5dcf3ee2 sfdp zynq> cat jedec_id c28339 zynq> cat manufacturer macronix zynq> cat partname mx25um25345g zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff0000000000000000ffffffff ffffffffe5208affffffff0f00ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff87690100821200d2cc02673830b030b0f4bdd55c 000000ff101000200000000000007c234800000000008888000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 040900001445988043060f0021dcffff zynq> md5sum sfdp 950e623745a002e1747008592e6dbdf9 sfdp zynq> cat jedec_id c28439 zynq> cat manufacturer macronix zynq> cat partname mx25uw25345g zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff0000000000000000ffffffff ffffffffe5208affffffff0f00ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff87790100841200d2cc04674630b030b0f4bdd55c 000000ff101000200000000000007c234800000000008888000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 000a00001445988043060f0021dcffff zynq> md5sum sfdp f7712440f8ce0adb538dfa0c10579c79 sfdp zynq> cat jedec_id c28138 zynq> cat manufacturer macronix zynq> cat partname mx25uw12845g zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff000000000000000000000000 00000000e5208affffffff0700ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff8b7901008f1200c9cc04674630b030b0f4bdd55c 000000ff101000200000000000007ca34800000000008888000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 000a00001445988043060f0021dcffff zynq> md5sum sfdp 9eacff90d7aa7cf737b970e0f2a7f2c6 sfdp zynq> cat jedec_id c28438 zynq> cat manufacturer macronix zynq> cat partname mx25uw12345g zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff0000000000000000ffffffff ffffffffe5208affffffff0700ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff8b7901008f1200c9cc04674630b030b0f4bdd55c 000000ff101000200000000000007c234800000000008888000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 000a00001445988043060f0021dcffff zynq> md5sum sfdp a3eb609c08894c84270ad06efc03766c sfdp zynq> cat jedec_id c28137 zynq> cat manufacturer macronix zynq> cat partname mx25uw6445g zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff0000000000000000ffffffff ffffffffe5208affffffff0300ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff897901008d1200c4cc04674630b030b0f4bdd55c 000000ff101000200000000000007ca34800000000008888000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 000a00001445988043060f0021dcffff zynq> md5sum sfdp b09aeedb0cfd0f77adc7e08592d295a9 sfdp zynq> cat jedec_id c28437 zynq> cat manufacturer macronix zynq> cat partname mx25uw6345g zynq> xxd -p sfdp 53464450080104fd00070114400000ff8701011c900000ff0a0001080001 00ff05000105200100ff84000102340100ff0000000000000000ffffffff ffffffffe5208affffffff0300ff00ff00ff00ffeeffffffffff00ffffff 00ff0c2010d800ff00ff8b7901008f1200c4cc04674630b030b0f4bdd55c 000000ff101000200000000000007c234800000000008888000000000000 00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8 727103b80000000090a3188200c069960000000000000000727100987271 00b8727100990000000072710098727100f872710099727100f900000000 00000000011501d0727106d8000086500000060100000000020001030002 00000000060100000000000072060002000000eec0697272717100d8f7f6 000a00001445988043060f0021dcffff zynq> md5sum sfdp c6fb57b8fdd4c35b5f0dacc4a1f7d4f4 sfdp Signed-off-by: JaimeLiao --- drivers/mtd/spi-nor/macronix.c | 45 ++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index 28c49c98503a..1ccea31ae64a 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -121,6 +121,51 @@ static const struct flash_info macronix_nor_parts[] = { { "mx66u2g45g", INFO(0xc2253c, 0, 64 * 1024, 4096) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, + { "mx66uw2g345gx0", INFOB(0xc2943c, 0, 0, 0, 4) + PARSE_SFDP + FLAGS(SPI_NOR_RWW) }, + { "mx66lm1g45g", INFOB(0xc2853b, 0, 0, 0, 4) + PARSE_SFDP }, + { "mx25lm51245g", INFOB(0xc2853a, 0, 0, 0, 4) + PARSE_SFDP }, + { "mx25lw51245g", INFOB(0xc2863a, 0, 0, 0, 4) + PARSE_SFDP + FLAGS(SPI_NOR_RWW) }, + { "mx25lm25645g", INFOB(0xc28539, 0, 0, 0, 4) + PARSE_SFDP }, + { "mx66uw2g345g", INFOB(0xc2843c, 0, 0, 0, 4) + PARSE_SFDP + FLAGS(SPI_NOR_RWW) }, + { "mx66um1g45g", INFOB(0xc2803b, 0, 0, 0, 4) + PARSE_SFDP }, + { "mx66uw1g45g", INFOB(0xc2813b, 0, 0, 0, 4) + PARSE_SFDP + FLAGS(SPI_NOR_RWW) }, + { "mx25uw51345g", INFOB(0xc2843a, 0, 0, 0, 4) + PARSE_SFDP + FLAGS(SPI_NOR_RWW) }, + { "mx25um25645g", INFO(0xc28039, 0, 0, 0) + PARSE_SFDP }, + { "mx25uw25645g", INFO(0xc28139, 0, 0, 0) + PARSE_SFDP + FLAGS(SPI_NOR_RWW) }, + { "mx25um25345g", INFO(0xc28339, 0, 0, 0) + PARSE_SFDP }, + { "mx25uw25345g", INFOB(0xc28439, 0, 0, 0, 4) + PARSE_SFDP + FLAGS(SPI_NOR_RWW) }, + { "mx25uw12845g", INFOB(0xc28138, 0, 0, 0, 4) + PARSE_SFDP + FLAGS(SPI_NOR_RWW) }, + { "mx25uw12345g", INFOB(0xc28438, 0, 0, 0, 4) + PARSE_SFDP + FLAGS(SPI_NOR_RWW) }, + { "mx25uw6445g", INFOB(0xc28137, 0, 0, 0, 4) + PARSE_SFDP + FLAGS(SPI_NOR_RWW) }, + { "mx25uw6345g", INFOB(0xc28437, 0, 0, 0, 4) + PARSE_SFDP + FLAGS(SPI_NOR_RWW) }, }; static int macronix_nor_octal_dtr_en(struct spi_nor *nor) From patchwork Fri Sep 8 06:43:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: JaimeLiao There are NOR flashes (Macronix) that swap the bytes on a 16-bit boundary when configured in Octal DTR mode. The byte order of 16-bit words is swapped when read or written in Octal Double Transfer Rat [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:532 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [jaimeliao.tw[at]gmail.com] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: JaimeLiao There are NOR flashes (Macronix) that swap the bytes on a 16-bit boundary when configured in Octal DTR mode. The byte order of 16-bit words is swapped when read or written in Octal Double Transfer Rate (DTR) mode compared to Single Transfer Rate (STR) modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses 8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2. Swapping the bytes may introduce some endianness problems. It can affect the boot sequence if the entire boot sequence is not handled in either 8D-8D-8D mode or 1-1-1 mode. So we must swap the bytes back to have the same byte order as in STR modes. Fortunately there are controllers that could swap the bytes back at runtime, addressing the flash's endiannesses requirements. Provide a way for the upper layers to specify the byte order in Octal DTR mode. Merge Tudor's patch and add modifications for suiting newer version of Linux kernel. Signed-off-by: Tudor Ambarus Signed-off-by: JaimeLiao --- drivers/spi/spi-mem.c | 4 ++++ include/linux/spi/spi-mem.h | 6 ++++++ 2 files changed, 10 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index edd7430d4c05..9c03b5617fff 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -172,6 +172,10 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, if (!spi_mem_controller_is_capable(ctlr, dtr)) return false; + if (op->data.dtr_swab16 && + !(spi_mem_controller_is_capable(ctlr, dtr_swab16))) + return false; + if (op->cmd.nbytes != 2) return false; } else { diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 6b0a7dc48a4b..d4935c5c3c7a 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -89,6 +89,8 @@ enum spi_mem_data_dir { * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not * @data.buswidth: number of IO lanes used to send/receive the data * @data.dtr: whether the data should be sent in DTR mode or not + * @data.dtr_swab16: whether the byte order of 16-bit words is swapped when read + * or written in Octal DTR mode compared to STR mode. * @data.ecc: whether error correction is required or not * @data.dir: direction of the transfer * @data.nbytes: number of data bytes to send/receive. Can be zero if the @@ -123,6 +125,7 @@ struct spi_mem_op { struct { u8 buswidth; u8 dtr : 1; + u8 dtr_swab16 : 1; u8 ecc : 1; u8 __pad : 6; enum spi_mem_data_dir dir; @@ -294,10 +297,13 @@ struct spi_controller_mem_ops { /** * struct spi_controller_mem_caps - SPI memory controller capabilities * @dtr: Supports DTR operations + * @dtr_swab16: Supports swapping bytes on a 16 bit boundary when configured in + * Octal DTR * @ecc: Supports operations with error correction */ struct spi_controller_mem_caps { bool dtr; + bool dtr_swab16; bool ecc; }; From patchwork Fri Sep 8 06:43:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liao jaime X-Patchwork-Id: 1831313 X-Patchwork-Delegate: tudor.ambarus@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=u44SPGbD; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: JaimeLiao Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR. The byte order of 16-bit words is swapped when read or written in 8D-8D-8D mode compared to STR modes. Allow operations to speci [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2001:4860:4864:20:0:0:0:2b listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [jaimeliao.tw[at]gmail.com] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: JaimeLiao Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR. The byte order of 16-bit words is swapped when read or written in 8D-8D-8D mode compared to STR modes. Allow operations to specify the byte order in DTR mode, so that controllers can swap the bytes back at run-time to address the flash's endianness requirements, if they are capable. If the controllers are not capable of swapping the bytes, the protocol is downgrade via spi_nor_spimem_adjust_hwcaps(). When available, the swapping of the bytes is always done regardless if it's a data or register access, so that we comply with the JESD216 requirements: "Byte order of 16-bit words is swapped when read in 8D-8D-8D mode compared to 1-1-1". Merge Tudor's patch and add modifications for suiting newer version of Linux kernel. Signed-off-by: Tudor Ambarus Signed-off-by: JaimeLiao --- drivers/mtd/spi-nor/core.c | 8 ++++++++ drivers/mtd/spi-nor/core.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 7ee624b16e17..83e7b7ff89ee 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -70,6 +70,13 @@ static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor, } } +static inline bool spi_nor_is_octal_dtr_swab16(const struct spi_nor *nor, + enum spi_nor_protocol proto) +{ + return (proto == SNOR_PROTO_8_8_8_DTR) && + (nor->flags & SNOR_F_DTR_SWAB16); +} + /** * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op. * @nor: pointer to a 'struct spi_nor' @@ -105,6 +112,7 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, op->addr.dtr = true; op->dummy.dtr = true; op->data.dtr = true; + op->data.dtr_swab16 = spi_nor_is_octal_dtr_swab16(nor, proto); /* 2 bytes per clock cycle in DTR mode. */ op->dummy.nbytes *= 2; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 92cbc2d3f7fe..7ff4c96fe21e 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -133,6 +133,7 @@ enum spi_nor_option_flags { SNOR_F_RWW = BIT(14), SNOR_F_ECC = BIT(15), SNOR_F_NO_WP = BIT(16), + SNOR_F_DTR_SWAB16 = BIT(17), }; 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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id w24-20020aa78598000000b0064378c52398sm681847pfn.25.2023.09.07.23.43.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Sep 2023 23:43:12 -0700 (PDT) Received: from hqs-appsw-appswa2.mp600.macronix.com (linux-patcher [172.17.236.35]) by twhmp6px (Postfix) with ESMTPS id 6039880E29; Fri, 8 Sep 2023 14:45:09 +0800 (CST) From: Jaime Liao To: linux-mtd@lists.infradead.org, tudor.ambarus@linaro.org, pratyush@kernel.org, michael@walle.cc, miquel.raynal@bootlin.com Cc: leoyu@mxic.com.tw, jaimeliao@mxic.com.tw Subject: [PATCH v4 6/6] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT Date: Fri, 8 Sep 2023 14:43:04 +0800 Message-Id: <20230908064304.27757-7-jaimeliao.tw@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908064304.27757-1-jaimeliao.tw@gmail.com> References: <20230908064304.27757-1-jaimeliao.tw@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230907_234317_757976_870DC6CD X-CRM114-Status: GOOD ( 11.97 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: JaimeLiao Parse BFPT in order to retrieve the byte order in 8D-8D-8D mode. Signed-off-by: Tudor Ambarus Signed-off-by: JaimeLiao --- drivers/mtd/spi-nor/sfdp.c | 4 ++++ drivers/mtd/spi-nor/sfdp.h | 1 + 2 files changed, 5 insertions(+) Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:435 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [jaimeliao.tw[at]gmail.com] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: JaimeLiao Parse BFPT in order to retrieve the byte order in 8D-8D-8D mode. Signed-off-by: Tudor Ambarus Signed-off-by: JaimeLiao --- drivers/mtd/spi-nor/sfdp.c | 4 ++++ drivers/mtd/spi-nor/sfdp.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index b3b11dfed789..2241207556bf 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -650,6 +650,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, return -EOPNOTSUPP; } + /* Byte order in 8D-8D-8D mode */ + if (bfpt.dwords[SFDP_DWORD(18)] & BFPT_DWORD18_BYTE_ORDER_SWAPPED) + nor->flags |= SNOR_F_DTR_SWAB16; + return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt); } diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h index 6eb99e1cdd61..eba760941d43 100644 --- a/drivers/mtd/spi-nor/sfdp.h +++ b/drivers/mtd/spi-nor/sfdp.h @@ -123,6 +123,7 @@ struct sfdp_bfpt { #define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */ #define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */ #define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */ +#define BFPT_DWORD18_BYTE_ORDER_SWAPPED BIT(31) /* Byte order of 16-bit words in 8D-8D-8D mode */ struct sfdp_parameter_header { u8 id_lsb;