From patchwork Wed Sep 6 09:40:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 1830343 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=dui8NIHK; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=infradead.org header.i=@infradead.org header.a=rsa-sha256 header.s=casper.20170209 header.b=BxJRxc92; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RggYv3c1jz1yh5 for ; Wed, 6 Sep 2023 21:46:11 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Wdfz0HoquuFv2DXHtTAtPPYgjHBUMrkNaU+6VBtraKY=; b=dui8NIHK+iPou1 3fXrSCEzPvMRyVfEqamdq26Us04CRhjPcV0l2TloNEe/R4sQ7lFZhteMnh3YiKDCvL21Hm7iBxC3v QJahGxBQUX5bjcX6axzcjLRnlMLWaCwKi0daYvs4IqfHQ6qea/q2j/lH+F/A2HVO75HSWYEvx/LWb 7jZksAczurtPxjJXjSopCKupkr6LNxCzjcNtPJqkrTMCSXFfQxF5fxM+fSayARdcDInHgCyBQ/Nne dK/KWzD778/mAmq8BWTckECmnARL+7T4y+CES4G4bAAqUBeMI9KpSOEVdK8ZjCQCGxosDcGxNWBXx vRwaqUO1XbPJWu3IuE9w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qdqyt-008x1z-34; Wed, 06 Sep 2023 11:45:59 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qdp3i-007yOj-0y for opensbi@bombadil.infradead.org; Wed, 06 Sep 2023 09:42:50 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Type:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From:Sender :Reply-To:Content-ID:Content-Description; bh=KfPD3rYcIN9BQpXyxaae0phH7qSEe7zIP9jr4Eguyn0=; b=BxJRxc92xbaGEXlHWgf36X0hw7 A/ojz0zKeDKaO/Rx5dNGCuJ1GMmM0d1AACbjlGH52qgqotoKVAWcbnUPI96vj9TYCI7GJPcE7wLVJ EyOJDuqqyLpzl3+sUEmRoQF+QZ0YX0vSG3hJzm7eUrjLevaQbDPKaMKNcXASqLY//AM8ujjTpgkRk OM4Q5hKpao5Ye3TQKT+M2GmKX3Eub/GPGebdrJAmpvKAkeTNggEqLqKKVvqmJBZ5aH1TQgw92Yc/9 aySdFP8SMiuJ/CiAXK2+1rBdyML1JfMm6O0c3rRQcu7V03k31AZSGmuVYmGNecpJD2TrM1wH78r3q /qLRxT6Q==; Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by casper.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1qdp3b-0019vM-Mq for opensbi@lists.infradead.org; Wed, 06 Sep 2023 09:42:48 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3869g9bT000454; Wed, 6 Sep 2023 17:42:09 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 6 Sep 2023 17:42:05 +0800 From: Yu Chien Peter Lin To: CC: , , , , , , , , Yu Chien Peter Lin Subject: [PATCH 1/6] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device Date: Wed, 6 Sep 2023 17:40:46 +0800 Message-ID: <20230906094051.3957564-2-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230906094051.3957564-1-peterlin@andestech.com> References: <20230906094051.3957564-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3869g9bT000454 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230906_104244_502535_E94F0220 X-CRM114-Status: UNSURE ( 9.64 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.6 on casper.infradead.org summary: Content analysis details: (-0.9 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 TVD_RCVD_IP Message was received from an IP address -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 1.0 RDNS_DYNAMIC Delivered to internal network by host with dynamic-looking rDNS X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Add support for custom PMU extensions to set inhibit bits on custom CSRs by introducing the PMU device callback hw_counter_filter_mode(). This allows the perf tool to restrict event counting under a specified privileged mode by appending a modifier, e.g. perf record -e event:k to count events only happening in kernel mode. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang --- include/sbi/sbi_pmu.h | 6 ++++++ lib/sbi/sbi_pmu.c | 5 ++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h index 16f6877..d63149c 100644 --- a/include/sbi/sbi_pmu.h +++ b/include/sbi/sbi_pmu.h @@ -89,6 +89,12 @@ struct sbi_pmu_device { * Custom function returning the machine-specific irq-bit. */ int (*hw_counter_irq_bit)(void); + + /** + * Custom function to inhibit counting of events while in + * specified mode. + */ + void (*hw_counter_filter_mode)(unsigned long flags, int counter_index); }; /** Get the PMU platform device */ diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index e8bed49..cfe9b0c 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -594,7 +594,10 @@ static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx, pmu_dev->hw_counter_disable_irq(ctr_idx); /* Update the inhibit flags based on inhibit flags received from supervisor */ - pmu_update_inhibit_flags(flags, &mhpmevent_val); + if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF)) + pmu_update_inhibit_flags(flags, &mhpmevent_val); + if (pmu_dev && pmu_dev->hw_counter_filter_mode) + pmu_dev->hw_counter_filter_mode(flags, ctr_idx); #if __riscv_xlen == 32 csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF); From patchwork Wed Sep 6 09:40:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 1830294 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=Y/pEFzl6; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Rgcqc15BTz1ygc for ; Wed, 6 Sep 2023 19:42:52 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=VPdNh54l744Ob2G8KL8VuEqeOKH8IHT2CAF+s3KoVbM=; b=Y/pEFzl6XzLlJa 4mGSt3FSUDKI1ZGfr3vclUJBlWMjS6uZGq/gUO4G4jT7WMg6lGUJwAtSw8K39LVPDvHImpx8yKP2N zxTmp2FLxZ/pK+KbNreeL7TTeMLUzSYdY2w25Rla9VSI+D7d8U4ZuyWWn6NYQTd4qdAsF+Icx7O9N xfuZWO4pvhtSLweKpi2TcDUgldGgNPj9CHPxWnjrpGAQuk9Uo8LeuwQHPf6lHhKCn+gppeNl0A9lG hR+sidwCkQiYVFliuOITzIZnVTOncmRnbntszlyjRJzND/AgldLmaw5c5U5qUIQw8/Owx4dmZ7QiC hR5xigWL9+5wInqvlqrg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qdp3Q-007yHf-20; Wed, 06 Sep 2023 09:42:32 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qdp3M-007yEv-19 for opensbi@lists.infradead.org; Wed, 06 Sep 2023 09:42:30 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3869gEt3000731; Wed, 6 Sep 2023 17:42:14 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 6 Sep 2023 17:42:10 +0800 From: Yu Chien Peter Lin To: CC: , , , , , , , , Yu Chien Peter Lin Subject: [PATCH 2/6] platform: include: andes45: Add PMU related CSR defines Date: Wed, 6 Sep 2023 17:40:47 +0800 Message-ID: <20230906094051.3957564-3-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230906094051.3957564-1-peterlin@andestech.com> References: <20230906094051.3957564-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3869gEt3000731 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230906_024228_839554_10FD26CF X-CRM114-Status: UNSURE ( 7.05 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.4 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: This patch adds CSR for Andes PMU extension. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang --- platform/generic/include/andes/andes45.h | 26 ++++++++++++++++++++++++ 1 file chang [...] Content analysis details: (0.4 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 TVD_RCVD_IP Message was received from an IP address -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.4 RDNS_DYNAMIC Delivered to internal network by host with dynamic-looking rDNS X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org This patch adds CSR for Andes PMU extension. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang --- platform/generic/include/andes/andes45.h | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h index f570994..6b141cf 100644 --- a/platform/generic/include/andes/andes45.h +++ b/platform/generic/include/andes/andes45.h @@ -12,6 +12,17 @@ #define CSR_MDCM_CFG 0xfc1 #define CSR_MMSC_CFG 0xfc2 +/* Machine Trap Related Registers */ +#define CSR_MSLIDELEG 0x7d5 + +/* Counter Related Registers */ +#define CSR_MCOUNTERWEN 0x7ce +#define CSR_MCOUNTERINTEN 0x7cf +#define CSR_MCOUNTERMASK_M 0x7d1 +#define CSR_MCOUNTERMASK_S 0x7d2 +#define CSR_MCOUNTERMASK_U 0x7d3 +#define CSR_MCOUNTEROVF 0x7d4 + #define MICM_CFG_ISZ_OFFSET 6 #define MICM_CFG_ISZ_MASK (0x7 << MICM_CFG_ISZ_OFFSET) @@ -26,4 +37,19 @@ #define MCACHE_CTL_CCTL_SUEN_OFFSET 8 #define MCACHE_CTL_CCTL_SUEN_MASK (0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET) +/* Performance monitor */ +#define MMSC_CFG_PMNDS_MASK (1 << 15) +#define MIP_PMOVI (1 << 18) + +#ifndef __ASSEMBLER__ + +#define andes_pmu() \ +({ \ + (((csr_read(CSR_MMSC_CFG) & \ + MMSC_CFG_PMNDS_MASK) \ + && misa_extension('S')) ? true : false); \ +}) + +#endif /* __ASSEMBLER__ */ + #endif /* _RISCV_ANDES45_H */ From patchwork Wed Sep 6 09:40:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 1830298 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=YsZnD2b1; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=infradead.org header.i=@infradead.org header.a=rsa-sha256 header.s=casper.20170209 header.b=rimp0KYg; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; 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Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by casper.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1qdp3c-0019vT-0H for opensbi@lists.infradead.org; Wed, 06 Sep 2023 09:42:50 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3869gJe9000751; Wed, 6 Sep 2023 17:42:19 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 6 Sep 2023 17:42:15 +0800 From: Yu Chien Peter Lin To: CC: , , , , , , , , Yu Chien Peter Lin Subject: [PATCH 3/6] platform: andes: Add Andes custom PMU support Date: Wed, 6 Sep 2023 17:40:48 +0800 Message-ID: <20230906094051.3957564-4-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230906094051.3957564-1-peterlin@andestech.com> References: <20230906094051.3957564-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3869gJe9000751 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230906_104244_831236_7948543F X-CRM114-Status: GOOD ( 16.86 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.6 on casper.infradead.org summary: Content analysis details: (-0.9 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 TVD_RCVD_IP Message was received from an IP address -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 1.0 RDNS_DYNAMIC Delivered to internal network by host with dynamic-looking rDNS X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Before the ratification of Sscofpmf, the Andes PMU extension was designed to support the sampling and filtering of hardware performance counters, compatible with the current SBI PMU extension and Linux perf driver. This patch implements the PMU extension platform callback and PMU device callbacks to update the corresponding custom CSRs. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang --- platform/generic/andes/Kconfig | 4 + platform/generic/andes/andes_pmu.c | 85 ++++++++++++++++++++++ platform/generic/andes/objects.mk | 1 + platform/generic/include/andes/andes_pmu.h | 12 +++ 4 files changed, 102 insertions(+) create mode 100644 platform/generic/andes/andes_pmu.c create mode 100644 platform/generic/include/andes/andes_pmu.h diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig index a91fb9c..056327b 100644 --- a/platform/generic/andes/Kconfig +++ b/platform/generic/andes/Kconfig @@ -7,3 +7,7 @@ config ANDES45_PMA config ANDES_SBI bool "Andes SBI support" default n + +config ANDES_PMU + bool "Andes PMU support" + default n diff --git a/platform/generic/andes/andes_pmu.c b/platform/generic/andes/andes_pmu.c new file mode 100644 index 0000000..d2574c7 --- /dev/null +++ b/platform/generic/andes/andes_pmu.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Copyright (C) 2022 Andes Technology Corporation + * + */ +#include +#include +#include +#include +#include +#include + +static void andes_hw_counter_enable_irq(uint32_t ctr_idx) +{ + unsigned long mip_val; + + if (ctr_idx >= SBI_PMU_HW_CTR_MAX) + return; + + mip_val = csr_read(CSR_MIP); + if (!(mip_val & MIP_PMOVI)) + csr_clear(CSR_MCOUNTEROVF, BIT(ctr_idx)); + + csr_set(CSR_MCOUNTERINTEN, BIT(ctr_idx)); +} + +static void andes_hw_counter_disable_irq(uint32_t ctr_idx) +{ + csr_clear(CSR_MCOUNTERINTEN, BIT(ctr_idx)); +} + +static void andes_hw_counter_filter_mode(unsigned long flags, int ctr_idx) +{ + if (!flags) { + csr_write(CSR_MCOUNTERMASK_S, 0); + csr_write(CSR_MCOUNTERMASK_U, 0); + } + if (flags & SBI_PMU_CFG_FLAG_SET_UINH) { + csr_clear(CSR_MCOUNTERMASK_S, BIT(ctr_idx)); + csr_set(CSR_MCOUNTERMASK_U, BIT(ctr_idx)); + } + if (flags & SBI_PMU_CFG_FLAG_SET_SINH) { + csr_set(CSR_MCOUNTERMASK_S, BIT(ctr_idx)); + csr_clear(CSR_MCOUNTERMASK_U, BIT(ctr_idx)); + } +} + +static struct sbi_pmu_device andes_pmu = { + .name = "andes_pmu", + .hw_counter_enable_irq = andes_hw_counter_enable_irq, + .hw_counter_disable_irq = andes_hw_counter_disable_irq, + /* + * In andes_pmu_extensions_init(), we set mslideleg[18] for each + * hart instead of mideleg, so leave hw_counter_irq_bit() hook + * unimplemented. + */ + .hw_counter_irq_bit = NULL, + .hw_counter_filter_mode = andes_hw_counter_filter_mode +}; + +int andes_pmu_extensions_init(const struct fdt_match *match, + struct sbi_hart_features *hfeatures) +{ + if (andes_pmu()) { + /* + * It is not rational for a hardware to support + * both Andes PMU and standard Sscofpmf, as they + * serve the same purpose. + */ + if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(), + SBI_HART_EXT_SSCOFPMF)) + ebreak(); + + /* Machine counter write enable */ + csr_write(CSR_MCOUNTERWEN, 0xfffffffd); + /* disable HPM counter in M-mode */ + csr_write(CSR_MCOUNTERMASK_M, 0xfffffffd); + /* delegate S-mode local interrupt to S-mode */ + csr_write(CSR_MSLIDELEG, MIP_PMOVI); + + sbi_pmu_set_device(&andes_pmu); + } + + return 0; +} diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk index e8f86ea..6a8c66c 100644 --- a/platform/generic/andes/objects.mk +++ b/platform/generic/andes/objects.mk @@ -7,3 +7,4 @@ platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o platform-objs-$(CONFIG_ANDES_SBI) += andes/andes_sbi.o +platform-objs-$(CONFIG_ANDES_PMU) += andes/andes_pmu.o diff --git a/platform/generic/include/andes/andes_pmu.h b/platform/generic/include/andes/andes_pmu.h new file mode 100644 index 0000000..8a2e136 --- /dev/null +++ b/platform/generic/include/andes/andes_pmu.h @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: BSD-2-Clause + +#ifndef _RISCV_ANDES_PMU_H +#define _RISCV_ANDES_PMU_H + +#include +#include + +int andes_pmu_extensions_init(const struct fdt_match *match, + struct sbi_hart_features *hfeatures); + +#endif /* _RISCV_ANDES_PMU_H */ From patchwork Wed Sep 6 09:40:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 1830295 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=v5YLKeIB; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Rgcqd3bS4z1ygc for ; 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Wed, 06 Sep 2023 09:42:38 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qdp3S-007yI0-3B for opensbi@lists.infradead.org; Wed, 06 Sep 2023 09:42:36 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3869gOex001024; Wed, 6 Sep 2023 17:42:24 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 6 Sep 2023 17:42:20 +0800 From: Yu Chien Peter Lin To: CC: , , , , , , , , Yu Chien Peter Lin Subject: [PATCH 4/6] platform: andes: Enable Andes PMU for AE350 Date: Wed, 6 Sep 2023 17:40:49 +0800 Message-ID: <20230906094051.3957564-5-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230906094051.3957564-1-peterlin@andestech.com> References: <20230906094051.3957564-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3869gOex001024 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230906_024235_482589_04E46D24 X-CRM114-Status: UNSURE ( 7.61 ) X-CRM114-Notice: Please train this message. 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Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang --- platform/generic/Kconfig | 1 + platform/generic/andes/ae350.c | 2 ++ 2 files change [...] Content analysis details: (0.4 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 TVD_RCVD_IP Message was received from an IP address -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.4 RDNS_DYNAMIC Delivered to internal network by host with dynamic-looking rDNS X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Enable Andes PMU extension support for AE350 platforms. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang --- platform/generic/Kconfig | 1 + platform/generic/andes/ae350.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig index 72768ed..16c28fe 100644 --- a/platform/generic/Kconfig +++ b/platform/generic/Kconfig @@ -31,6 +31,7 @@ config PLATFORM_ALLWINNER_D1 config PLATFORM_ANDES_AE350 bool "Andes AE350 support" select SYS_ATCSMU + select ANDES_PMU default n config PLATFORM_RENESAS_RZFIVE diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c index 01bd02d..c8adb0d 100644 --- a/platform/generic/andes/ae350.c +++ b/platform/generic/andes/ae350.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -118,4 +119,5 @@ static const struct fdt_match andes_ae350_match[] = { const struct platform_override andes_ae350 = { .match_table = andes_ae350_match, .final_init = ae350_final_init, + .extensions_init = andes_pmu_extensions_init, }; From patchwork Wed Sep 6 09:40:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 1830296 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=J4WCVbHO; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Rgcql3m9Cz1ygc for ; Wed, 6 Sep 2023 19:42:59 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pf/rv9IUwN2zs3qWKZItge85w+Pf4Z+69wQMCKU6A1o=; b=J4WCVbHOV0biHa NoKRa02wr5TKASAXLRGFBpJsHTBK0md8vFi1Y5if7rwovYTEOLD3sB8rVcw0jlw8HtPBHwYN5IeGW mPjIPIjj+pD9BVgaeaF0gC6UjwUaa46yuoeszJAkDWAYNZpNjvRqOpMfzslKV7zn9aynhCBQoEbA5 ziklEsejYbeYLr3QMpzaZmETgclKSlFm982UlDfAgt+nBj8gN5LjfZjg9W6BCUl3lPleYxGoVVDhh W6tSLitEsZodtY+p15Z3oBNOQxqHI9sXpaCIOjA/UDSCkpcXdjczmPGvnkmK7sFfNMF+kdFmgo8WP 0bDgE+1fo36r04vJhdUw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qdp3b-007yM6-1f; Wed, 06 Sep 2023 09:42:43 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qdp3Y-007yKC-0W for opensbi@lists.infradead.org; Wed, 06 Sep 2023 09:42:41 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3869gTU1001048; Wed, 6 Sep 2023 17:42:29 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 6 Sep 2023 17:42:25 +0800 From: Yu Chien Peter Lin To: CC: , , , , , , , , Yu Chien Peter Lin Subject: [PATCH 5/6] platform: rzfive: Enable Andes PMU for RZ/Five Date: Wed, 6 Sep 2023 17:40:50 +0800 Message-ID: <20230906094051.3957564-6-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230906094051.3957564-1-peterlin@andestech.com> References: <20230906094051.3957564-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3869gTU1001048 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230906_024240_634856_7A2E719A X-CRM114-Status: UNSURE ( 6.99 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.4 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Enable Andes PMU extension support for RZ/Five. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang --- platform/generic/Kconfig | 1 + platform/generic/renesas/rzfive/rzfive.c | 2 ++ 2 fi [...] Content analysis details: (0.4 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 TVD_RCVD_IP Message was received from an IP address -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.4 RDNS_DYNAMIC Delivered to internal network by host with dynamic-looking rDNS X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Enable Andes PMU extension support for RZ/Five. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang --- platform/generic/Kconfig | 1 + platform/generic/renesas/rzfive/rzfive.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig index 16c28fe..e6e7e94 100644 --- a/platform/generic/Kconfig +++ b/platform/generic/Kconfig @@ -38,6 +38,7 @@ config PLATFORM_RENESAS_RZFIVE bool "Renesas RZ/Five support" select ANDES45_PMA select ANDES_SBI + select ANDES_PMU default n config PLATFORM_SIFIVE_FU540 diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c index a69797b..7b65a50 100644 --- a/platform/generic/renesas/rzfive/rzfive.c +++ b/platform/generic/renesas/rzfive/rzfive.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -57,4 +58,5 @@ const struct platform_override renesas_rzfive = { .early_init = renesas_rzfive_early_init, .final_init = renesas_rzfive_final_init, .vendor_ext_provider = andes_sbi_vendor_ext_provider, + .extensions_init = andes_pmu_extensions_init, }; From patchwork Wed Sep 6 09:40:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 1830297 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=NU73Gwm5; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=patchwork.ozlabs.org) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Rgcqq5cwDz1ygc for ; Wed, 6 Sep 2023 19:43:03 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aUjCwXO8T/RV+LRr73i0yE/fZOtkkpgph+kFo4R82hY=; b=NU73Gwm5q4A2TH rcN5A7wAIE+X4AO9C1TLu4BdkA58sTKKgmtr8HOn7yxhwFGnfN7FIg0dIPh4DdMSCqEAQXbSu/XQc iiDx+Vvp/ggCo4rdX6VCUFuWRIZcO2yjBP8VnPbiiMfdYuaHnKNhE8odcQgMX6BqV0VFxcyNkcFEq 4etYlUoRTmUi6B0l7Pn0grubjwhaESNdDBN+GTDfoV4OnIizJqN2RQ5asOqxmQWdspvtvpAfiXUuw BgGFMpd+edYB1Sz9vjmiPNjCTTbd3kQJNcU2IRYPBtA2j+TpwKFlyEI5GWl2uO78x+H1GtL6DyRIr 1KVhFw6wb7XboZkwU7dw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qdp3h-007yOy-1E; Wed, 06 Sep 2023 09:42:49 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qdp3d-007yMH-1l for opensbi@lists.infradead.org; Wed, 06 Sep 2023 09:42:48 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3869gYdq001064; Wed, 6 Sep 2023 17:42:34 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 6 Sep 2023 17:42:30 +0800 From: Yu Chien Peter Lin To: CC: , , , , , , , , Yu Chien Peter Lin Subject: [PATCH 6/6] docs: pmu: Add Andes PMU node example Date: Wed, 6 Sep 2023 17:40:51 +0800 Message-ID: <20230906094051.3957564-7-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230906094051.3957564-1-peterlin@andestech.com> References: <20230906094051.3957564-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3869gYdq001064 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230906_024246_026902_D866799F X-CRM114-Status: UNSURE ( 8.04 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.4 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Add PMU node example for event index to counter index mapping and selector value translation of Andes' CPUs. Currently, there are 4 HPM counters that can be used to monitor all of the events for each hart. Content analysis details: (0.4 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 TVD_RCVD_IP Message was received from an IP address -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.4 RDNS_DYNAMIC Delivered to internal network by host with dynamic-looking rDNS X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Add PMU node example for event index to counter index mapping and selector value translation of Andes' CPUs. Currently, there are 4 HPM counters that can be used to monitor all of the events for each hart. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Locus Wei-Han Chen Reviewed-by: Leo Yu-Chi Liang --- docs/pmu_support.md | 87 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/docs/pmu_support.md b/docs/pmu_support.md index 8cfa08c..6d8fa9d 100644 --- a/docs/pmu_support.md +++ b/docs/pmu_support.md @@ -125,3 +125,90 @@ pmu { <0x0 0x2 0xffffffff 0xffffe0ff 0x18>; }; ``` + +### Example 3 + +``` +/* + * For Andes 45-series platforms. The encodings can be found in the + * "Machine Performance Monitoring Event Selector" section + * http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + */ +pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmevent = + <0x1 0x0000 0x10>, /* CPU_CYCLES -> Cycle count */ + <0x2 0x0000 0x20>, /* INSTRUCTIONS -> Retired instruction count */ + <0x3 0x0000 0x41>, /* CACHE_REFERENCES -> D-Cache access */ + <0x4 0x0000 0x51>, /* CACHE_MISSES -> D-Cache miss */ + <0x5 0x0000 0x80>, /* BRANCH_INSTRUCTIONS -> Conditional branch instruction count */ + <0x6 0x0000 0x02>, /* BRANCH_MISSES -> Misprediction of conditional branches */ + <0x10000 0x0000 0x61>, /* L1D_READ_ACCESS -> D-Cache load access */ + <0x10001 0x0000 0x71>, /* L1D_READ_MISS -> D-Cache load miss */ + <0x10002 0x0000 0x81>, /* L1D_WRITE_ACCESS -> D-Cache store access */ + <0x10003 0x0000 0x91>, /* L1D_WRITE_MISS -> D-Cache store miss */ + <0x10008 0x0000 0x21>, /* L1I_READ_ACCESS -> I-Cache access */ + <0x10009 0x0000 0x31>, /* L1I_READ_MISS -> I-Cache miss */ + <0x10018 0x0000 0x131>, /* DTLB_READ_ACCESS -> Main DTLB access */ + <0x10020 0x0000 0x111>; /* ITLB_READ_ACCESS -> Main ITLB access */ + riscv,event-to-mhpmcounters = <0x1 0x6 0x78>, + <0x10000 0x10003 0x78>, + <0x10008 0x10009 0x78>, + <0x10018 0x10018 0x78>, + <0x10020 0x10020 0x78>; + riscv,raw-event-to-mhpmcounters = + <0x0 0x10 0xffffffff 0xffffffff 0x78>, /* Cycle count */ + <0x0 0x20 0xffffffff 0xffffffff 0x78>, /* Retired instruction count */ + <0x0 0x30 0xffffffff 0xffffffff 0x78>, /* Integer load instruction count */ + <0x0 0x40 0xffffffff 0xffffffff 0x78>, /* Integer store instruction count */ + <0x0 0x50 0xffffffff 0xffffffff 0x78>, /* Atomic instruction count */ + <0x0 0x60 0xffffffff 0xffffffff 0x78>, /* System instruction count */ + <0x0 0x70 0xffffffff 0xffffffff 0x78>, /* Integer computational instruction count */ + <0x0 0x80 0xffffffff 0xffffffff 0x78>, /* Conditional branch instruction count */ + <0x0 0x90 0xffffffff 0xffffffff 0x78>, /* Taken conditional branch instruction count */ + <0x0 0xA0 0xffffffff 0xffffffff 0x78>, /* JAL instruction count */ + <0x0 0xB0 0xffffffff 0xffffffff 0x78>, /* JALR instruction count */ + <0x0 0xC0 0xffffffff 0xffffffff 0x78>, /* Return instruction count */ + <0x0 0xD0 0xffffffff 0xffffffff 0x78>, /* Control transfer instruction count */ + <0x0 0xE0 0xffffffff 0xffffffff 0x78>, /* EXEC.IT instruction count */ + <0x0 0xF0 0xffffffff 0xffffffff 0x78>, /* Integer multiplication instruction count */ + <0x0 0x100 0xffffffff 0xffffffff 0x78>, /* Integer division instruction count */ + <0x0 0x110 0xffffffff 0xffffffff 0x78>, /* Floating-point load instruction count */ + <0x0 0x120 0xffffffff 0xffffffff 0x78>, /* Floating-point store instruction count */ + <0x0 0x130 0xffffffff 0xffffffff 0x78>, /* Floating-point addition/subtraction instruction count */ + <0x0 0x140 0xffffffff 0xffffffff 0x78>, /* Floating-point multiplication instruction count */ + <0x0 0x150 0xffffffff 0xffffffff 0x78>, /* Floating-point fused multiply-add instruction count */ + <0x0 0x160 0xffffffff 0xffffffff 0x78>, /* Floating-point division or square-root instruction count */ + <0x0 0x170 0xffffffff 0xffffffff 0x78>, /* Other floating-point instruction count */ + <0x0 0x180 0xffffffff 0xffffffff 0x78>, /* Integer multiplication and add/sub instruction count */ + <0x0 0x190 0xffffffff 0xffffffff 0x78>, /* Retired operation count */ + <0x0 0x01 0xffffffff 0xffffffff 0x78>, /* ILM access */ + <0x0 0x11 0xffffffff 0xffffffff 0x78>, /* DLM access */ + <0x0 0x21 0xffffffff 0xffffffff 0x78>, /* I-Cache access */ + <0x0 0x31 0xffffffff 0xffffffff 0x78>, /* I-Cache miss */ + <0x0 0x41 0xffffffff 0xffffffff 0x78>, /* D-Cache access */ + <0x0 0x51 0xffffffff 0xffffffff 0x78>, /* D-Cache miss */ + <0x0 0x61 0xffffffff 0xffffffff 0x78>, /* D-Cache load access */ + <0x0 0x71 0xffffffff 0xffffffff 0x78>, /* D-Cache load miss */ + <0x0 0x81 0xffffffff 0xffffffff 0x78>, /* D-Cache store access */ + <0x0 0x91 0xffffffff 0xffffffff 0x78>, /* D-Cache store miss */ + <0x0 0xA1 0xffffffff 0xffffffff 0x78>, /* D-Cache writeback */ + <0x0 0xB1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for I-Cache fill data */ + <0x0 0xC1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for D-Cache fill data */ + <0x0 0xD1 0xffffffff 0xffffffff 0x78>, /* Uncached fetch data access from bus */ + <0x0 0xE1 0xffffffff 0xffffffff 0x78>, /* Uncached load data access from bus */ + <0x0 0xF1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for uncached fetch data from bus */ + <0x0 0x101 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for uncached load data from bus */ + <0x0 0x111 0xffffffff 0xffffffff 0x78>, /* Main ITLB access */ + <0x0 0x121 0xffffffff 0xffffffff 0x78>, /* Main ITLB miss */ + <0x0 0x131 0xffffffff 0xffffffff 0x78>, /* Main DTLB access */ + <0x0 0x141 0xffffffff 0xffffffff 0x78>, /* Main DTLB miss */ + <0x0 0x151 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for Main ITLB fill data */ + <0x0 0x161 0xffffffff 0xffffffff 0x78>, /* Pipeline stall cycles caused by Main DTLB miss */ + <0x0 0x171 0xffffffff 0xffffffff 0x78>, /* Hardware prefetch bus access */ + <0x0 0x181 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for source operand ready in the integer register file scoreboard */ + <0x0 0x02 0xffffffff 0xffffffff 0x78>, /* Misprediction of conditional branches */ + <0x0 0x12 0xffffffff 0xffffffff 0x78>, /* Misprediction of taken conditional branches */ + <0x0 0x22 0xffffffff 0xffffffff 0x78>; /* Misprediction of targets of Return instructions */ +}; +```