From patchwork Thu Aug 31 17:32:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edwin Lu X-Patchwork-Id: 1828457 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=0PwtVWoJ; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Rc7XY3M3Zz1yZs for ; Fri, 1 Sep 2023 03:32:43 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BBFDA3858002 for ; Thu, 31 Aug 2023 17:32:41 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by sourceware.org (Postfix) with ESMTPS id E2F3F3858D28 for ; Thu, 31 Aug 2023 17:32:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E2F3F3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1bee82fad0fso8380785ad.2 for ; Thu, 31 Aug 2023 10:32:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1693503146; x=1694107946; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=OOBt7vshoZPF5MioK0LoVScClqxUZTaugWg3HfFzSiU=; b=0PwtVWoJjZ9rN1bFh9IOowkUOenKpIt8Z/JYR8AfiIEQ+xAR6RarUt9cBSrigbpcci KLslt9inVUhZh+GIdjcSts368uZyKSVdy4CipPyUm3ca8gYTmZpDBqidLGJGY8gZhVa1 yD5HdpumZ9hHscteGdR6Isnc/cZhrVl0nSQqkiAPYJMWIeVKSJKwU5HRmpiR0zO/vEJE 57ZUeixHVJfNM2rg19xYhWLuV57W3ENo7Mxj3lrtAXcmRPkB1mHeaagbe8d13J8A6Cae oTX8a+HFn0gESx7kH+0XNXoI3RF70ZZTQ5NiSCb1PC3bRvm4OpvhOcPHduuYUJG8cO8M DF7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693503146; x=1694107946; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=OOBt7vshoZPF5MioK0LoVScClqxUZTaugWg3HfFzSiU=; b=RzTrAUs4J+DOnWmeoxEhaBqoJb/l8rSZ1NP/oLesv1pH2YxPaud6wUe0AJuG0nOD9g 8Ik8ceEMraH5PvyAo0oYpGL5gXWQRndL6wpdkKOiEbITdoJ+g+H+TzpTacGUcWAyzK69 Ny86typXWw7Nad5iYhsMNzig6ER/nahztJfTnE7HqYGSNszKNGpwKYJAJPv2TfH9LmXy +Dfev3fwVFuCoGY6wxD+VLQj1yGsej/ZMix8X9yY9+jeY+U0wiIXaeQRszqRUJo0bVbk xrhKXPzW8S3RdALSDUgQ370jFdAqvRtAWpo8Vzqjp0FF47K5cFGtXsq21HWi7ByUdW9A ewKQ== X-Gm-Message-State: AOJu0Yyf3ZRSa6Wtrbtgr+BKu6nMiEBYYCiLuOq5g2WQj3VfYPtwJzsu sABmHWl6xRn2KN9xWb5lKMWOj7z6E+mNqRHp3D8= X-Google-Smtp-Source: AGHT+IGxNBmBcl5SeF5VhSVa6H/jM6zerHxUkY63lQWKA7GdrQ05FRmzAHQDFD2lW6EX//WlBaSr2A== X-Received: by 2002:a17:902:b490:b0:1b8:b3f9:58e5 with SMTP id y16-20020a170902b49000b001b8b3f958e5mr322369plr.38.1693503145550; Thu, 31 Aug 2023 10:32:25 -0700 (PDT) Received: from ewlu.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id 21-20020a170902ee5500b001b03cda6389sm1500569plo.10.2023.08.31.10.32.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Aug 2023 10:32:25 -0700 (PDT) From: Edwin Lu To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Add Types to Un-Typed Risc-v Instructions: Date: Thu, 31 Aug 2023 10:32:01 -0700 Message-ID: <20230831173218.583040-1-ewlu@rivosinc.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Spam-Status: No, score=-13.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gnu-toolchain@rivosinc.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Related Discussion: https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5eb2@gmail.com/ This patch updates the riscv instructions to ensure that no insn is left without a type attribute. Added new types: "trap" (self explanatory) and "cbo" (for cache related instructions) Tested for regressions using rv32/64 multilib for linux/newlib. Also tested rv32/64 gcv for linux. gcc/Changelog: * config/riscv/riscv.md: Update/Add types Signed-off-by: Edwin Lu --- gcc/config/riscv/riscv.md | 112 ++++++++++++++++++++++++++++---------- 1 file changed, 82 insertions(+), 30 deletions(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 4041875e0e3..d80b6938f84 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -303,12 +303,14 @@ (define_attr "ext_enabled" "no,yes" ;; auipc integer addition to PC ;; sfb_alu SFB ALU instruction ;; nop no operation +;; trap trap instruction ;; ghost an instruction that produces no real code ;; bitmanip bit manipulation instructions ;; clmul clmul, clmulh, clmulr ;; rotate rotation instructions ;; atomic atomic instructions ;; condmove conditional moves +;; cbo cache block instructions ;; crypto cryptography instructions ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. ;; rdvlenb vector byte length vlenb csrr read @@ -417,9 +419,9 @@ (define_attr "ext_enabled" "no,yes" (define_attr "type" "unknown,branch,jump,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, - fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate, - clmul,min,max,minu,maxu,clz,ctz,cpop, - atomic,condmove,crypto,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl, + fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip, + rotate,clmul,min,max,minu,maxu,clz,ctz,cpop, + atomic,condmove,cbo,crypto,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl, vlde,vste,vldm,vstm,vlds,vsts, vldux,vldox,vstux,vstox,vldff,vldr,vstr, vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff, @@ -1652,6 +1654,7 @@ (define_insn_and_split "*zero_extendsidi2_internal" (lshiftrt:DI (match_dup 0) (const_int 32)))] { operands[1] = gen_lowpart (DImode, operands[1]); } [(set_attr "move_type" "shift_shift,load") + (set_attr "type" "load") (set_attr "mode" "DI")]) (define_expand "zero_extendhi2" @@ -1680,6 +1683,7 @@ (define_insn_and_split "*zero_extendhi2" operands[2] = GEN_INT(GET_MODE_BITSIZE(mode) - 16); } [(set_attr "move_type" "shift_shift,load") + (set_attr "type" "load") (set_attr "mode" "")]) (define_insn "zero_extendqi2" @@ -1691,6 +1695,7 @@ (define_insn "zero_extendqi2" andi\t%0,%1,0xff lbu\t%0,%1" [(set_attr "move_type" "andi,load") + (set_attr "type" "multi") (set_attr "mode" "")]) ;; @@ -1709,6 +1714,7 @@ (define_insn "extendsidi2" sext.w\t%0,%1 lw\t%0,%1" [(set_attr "move_type" "move,load") + (set_attr "type" "multi") (set_attr "mode" "DI")]) (define_expand "extend2" @@ -1736,6 +1742,7 @@ (define_insn_and_split "*extend2" - GET_MODE_BITSIZE (mode)); } [(set_attr "move_type" "shift_shift,load") + (set_attr "type" "load") (set_attr "mode" "SI")]) (define_insn "extendhfsf2" @@ -1784,6 +1791,7 @@ (define_insn "*movhf_hardfloat" || reg_or_0_operand (operands[1], HFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") + (set_attr "type" "fmove") (set_attr "mode" "HF")]) (define_insn "*movhf_softfloat" @@ -1794,6 +1802,7 @@ (define_insn "*movhf_softfloat" || reg_or_0_operand (operands[1], HFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "fmove,move,load,store,mtc,mfc") + (set_attr "type" "fmove") (set_attr "mode" "HF")]) ;; @@ -1888,6 +1897,7 @@ (define_insn "got_load" "" "la\t%0,%1" [(set_attr "got" "load") + (set_attr "type" "load") (set_attr "mode" "")]) (define_insn "tls_add_tp_le" @@ -1910,6 +1920,7 @@ (define_insn "got_load_tls_gd" "" "la.tls.gd\t%0,%1" [(set_attr "got" "load") + (set_attr "type" "load") (set_attr "mode" "")]) (define_insn "got_load_tls_ie" @@ -1920,6 +1931,7 @@ (define_insn "got_load_tls_ie" "" "la.tls.ie\t%0,%1" [(set_attr "got" "load") + (set_attr "type" "load") (set_attr "mode" "")]) (define_insn "auipc" @@ -1989,7 +2001,8 @@ (define_insn_and_split "*mvconst_internal" riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]), mode); DONE; -}) +} +[(set_attr "type" "move")]) ;; 64-bit integer moves @@ -2011,6 +2024,7 @@ (define_insn "*movdi_32bit" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb") (set_attr "mode" "DI") + (set_attr "type" "move") (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")]) (define_insn "*movdi_64bit" @@ -2022,6 +2036,7 @@ (define_insn "*movdi_64bit" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb") (set_attr "mode" "DI") + (set_attr "type" "move") (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")]) ;; 32-bit Integer moves @@ -2045,6 +2060,7 @@ (define_insn "*movsi_internal" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore,rdvlenb") (set_attr "mode" "SI") + (set_attr "type" "move") (set_attr "ext" "base,base,base,base,f,f,f,f,vector")]) ;; 16-bit Integer moves @@ -2071,6 +2087,7 @@ (define_insn "*movhi_internal" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb") (set_attr "mode" "HI") + (set_attr "type" "move") (set_attr "ext" "base,base,base,base,f,f,vector")]) ;; HImode constant generation; see riscv_move_integer for details. @@ -2114,6 +2131,7 @@ (define_insn "*movqi_internal" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb") (set_attr "mode" "QI") + (set_attr "type" "move") (set_attr "ext" "base,base,base,base,f,f,vector")]) ;; 32-bit floating point moves @@ -2135,6 +2153,7 @@ (define_insn "*movsf_hardfloat" || reg_or_0_operand (operands[1], SFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") + (set_attr "type" "fmove") (set_attr "mode" "SF")]) (define_insn "*movsf_softfloat" @@ -2145,6 +2164,7 @@ (define_insn "*movsf_softfloat" || reg_or_0_operand (operands[1], SFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,load,store") + (set_attr "type" "fmove") (set_attr "mode" "SF")]) ;; 64-bit floating point moves @@ -2169,6 +2189,7 @@ (define_insn "*movdf_hardfloat_rv32" || reg_or_0_operand (operands[1], DFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") + (set_attr "type" "fmove") (set_attr "mode" "DF")]) (define_insn "*movdf_hardfloat_rv64" @@ -2179,6 +2200,7 @@ (define_insn "*movdf_hardfloat_rv64" || reg_or_0_operand (operands[1], DFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") + (set_attr "type" "fmove") (set_attr "mode" "DF")]) (define_insn "*movdf_softfloat" @@ -2189,6 +2211,7 @@ (define_insn "*movdf_softfloat" || reg_or_0_operand (operands[1], DFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,load,store") + (set_attr "type" "fmove") (set_attr "mode" "DF")]) (define_insn "movsidf2_low_rv32" @@ -2269,17 +2292,20 @@ (define_expand "clear_cache" (define_insn "fence" [(unspec_volatile [(const_int 0)] UNSPECV_FENCE)] "" - "%|fence%-") + "%|fence%-" + [(set_attr "type" "atomic")]) (define_insn "fence_i" [(unspec_volatile [(const_int 0)] UNSPECV_FENCE_I)] "TARGET_ZIFENCEI" - "fence.i") + "fence.i" + [(set_attr "type" "atomic")]) (define_insn "riscv_pause" [(unspec_volatile [(const_int 0)] UNSPECV_PAUSE)] "" - "* return TARGET_ZIHINTPAUSE ? \"pause\" : \".insn\t0x0100000f\";") + "* return TARGET_ZIHINTPAUSE ? \"pause\" : \".insn\t0x0100000f\";" + [(set_attr "type" "atomic")]) ;; ;; .................... @@ -2531,7 +2557,8 @@ (define_insn_and_split "*branch_shiftedarith_equals_zero" operands[6] = GEN_INT (trailing); operands[7] = GEN_INT (mask >> trailing); -}) +} +[(set_attr "type" "branch")]) (define_insn_and_split "*branch_shiftedmask_equals_zero" [(set (pc) @@ -2558,7 +2585,8 @@ (define_insn_and_split "*branch_shiftedmask_equals_zero" operands[6] = GEN_INT (leading); operands[7] = GEN_INT (leading + trailing); -}) +} +[(set_attr "type" "branch")]) (define_insn "*branch" [(set (pc) @@ -2669,7 +2697,8 @@ (define_insn_and_split "*branch_on_bit" operands[0] = gen_rtx_GE (mode, operands[4], const0_rtx); else operands[0] = gen_rtx_LT (mode, operands[4], const0_rtx); -}) +} +[(set_attr "type" "branch")]) (define_insn_and_split "*branch_on_bit_range" [(set (pc) @@ -2694,7 +2723,8 @@ (define_insn_and_split "*branch_on_bit_range" (pc)))] { operands[3] = GEN_INT (GET_MODE_BITSIZE (mode) - INTVAL (operands[3])); -}) +} +[(set_attr "type" "branch")]) ;; ;; .................... @@ -2997,13 +3027,15 @@ (define_insn "eh_set_lr_si" [(unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_EH_RETURN) (clobber (match_scratch:SI 1 "=&r"))] "! TARGET_64BIT" - "#") + "#" + [(set_attr "type" "jump")]) (define_insn "eh_set_lr_di" [(unspec [(match_operand:DI 0 "register_operand" "r")] UNSPEC_EH_RETURN) (clobber (match_scratch:DI 1 "=&r"))] "TARGET_64BIT" - "#") + "#" + [(set_attr "type" "jump")]) (define_split [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN) @@ -3021,7 +3053,8 @@ (define_insn_and_split "eh_return_internal" "#" "epilogue_completed" [(const_int 0)] - "riscv_expand_epilogue (EXCEPTION_RETURN); DONE;") + "riscv_expand_epilogue (EXCEPTION_RETURN); DONE;" + [(set_attr "type" "jump")]) ;; ;; .................... @@ -3155,7 +3188,8 @@ (define_insn "nop" (define_insn "trap" [(trap_if (const_int 1) (const_int 0))] "" - "ebreak") + "ebreak" + [(set_attr "type" "trap")]) ;; Must use the registers that we save to prevent the rename reg optimization ;; pass from using them before the gpr_save pattern when shrink wrapping @@ -3166,41 +3200,48 @@ (define_insn "gpr_save" [(unspec_volatile [(match_operand 0 "const_int_operand")] UNSPECV_GPR_SAVE)])] "" - "call\tt0,__riscv_save_%0") + "call\tt0,__riscv_save_%0" + [(set_attr "type" "call")]) (define_insn "gpr_restore" [(unspec_volatile [(match_operand 0 "const_int_operand")] UNSPECV_GPR_RESTORE)] "" - "tail\t__riscv_restore_%0") + "tail\t__riscv_restore_%0" + [(set_attr "type" "call")]) (define_insn "gpr_restore_return" [(return) (use (match_operand 0 "pmode_register_operand" "")) (const_int 0)] "" - "") + "" + [(set_attr "type" "jump")]) (define_insn "riscv_frcsr" [(set (match_operand:SI 0 "register_operand" "=r") (unspec_volatile [(const_int 0)] UNSPECV_FRCSR))] "TARGET_HARD_FLOAT || TARGET_ZFINX" - "frcsr\t%0") + "frcsr\t%0" + [(set_attr "type" "fmove")]) (define_insn "riscv_fscsr" [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] UNSPECV_FSCSR)] "TARGET_HARD_FLOAT || TARGET_ZFINX" - "fscsr\t%0") + "fscsr\t%0" + [(set_attr "type" "fmove")]) (define_insn "riscv_frflags" [(set (match_operand:SI 0 "register_operand" "=r") (unspec_volatile [(const_int 0)] UNSPECV_FRFLAGS))] "TARGET_HARD_FLOAT || TARGET_ZFINX" - "frflags\t%0") + "frflags\t%0" + [(set_attr "type" "fmove")]) (define_insn "riscv_fsflags" [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSFLAGS)] "TARGET_HARD_FLOAT || TARGET_ZFINX" - "fsflags%i0\t%0") + "fsflags%i0\t%0" + [(set_attr "type" "fmove")]) (define_insn "*riscv_fsnvsnan2" [(unspec_volatile [(match_operand:ANYF 0 "register_operand" "f") @@ -3215,19 +3256,22 @@ (define_insn "riscv_mret" [(return) (unspec_volatile [(const_int 0)] UNSPECV_MRET)] "" - "mret") + "mret" + [(set_attr "type" "jump")]) (define_insn "riscv_sret" [(return) (unspec_volatile [(const_int 0)] UNSPECV_SRET)] "" - "sret") + "sret" + [(set_attr "type" "jump")]) (define_insn "riscv_uret" [(return) (unspec_volatile [(const_int 0)] UNSPECV_URET)] "" - "uret") + "uret" + [(set_attr "type" "jump")]) (define_insn "stack_tie" [(set (mem:BLK (scratch)) @@ -3236,7 +3280,8 @@ (define_insn "stack_tie" UNSPEC_TIE))] "" "" - [(set_attr "length" "0")] + [(set_attr "type" "ghost") + (set_attr "length" "0")] ) ;; This fixes a failure with gcc.c-torture/execute/pr64242.c at -O2 for a @@ -3294,7 +3339,8 @@ (define_insn "stack_protect_set_" (set (match_scratch:GPR 2 "=&r") (const_int 0))] "" "\t%2, %1\;\t%2, %0\;li\t%2, 0" - [(set_attr "length" "12")]) + [(set_attr "type" "multi") + (set_attr "length" "12")]) (define_expand "stack_protect_test" [(match_operand 0 "memory_operand") @@ -3333,13 +3379,15 @@ (define_insn "stack_protect_test_" (clobber (match_scratch:GPR 3 "=&r"))] "" "\t%3, %1\;\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0" - [(set_attr "length" "12")]) + [(set_attr "type" "multi") + (set_attr "length" "12")]) (define_insn "riscv_clean_" [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] UNSPECV_CLEAN)] "TARGET_ZICBOM" "cbo.clean\t%a0" + [(set_attr "type" "cbo")] ) (define_insn "riscv_flush_" @@ -3347,6 +3395,7 @@ (define_insn "riscv_flush_" UNSPECV_FLUSH)] "TARGET_ZICBOM" "cbo.flush\t%a0" + [(set_attr "type" "cbo")] ) (define_insn "riscv_inval_" @@ -3354,6 +3403,7 @@ (define_insn "riscv_inval_" UNSPECV_INVAL)] "TARGET_ZICBOM" "cbo.inval\t%a0" + [(set_attr "type" "cbo")] ) (define_insn "riscv_zero_" @@ -3361,6 +3411,7 @@ (define_insn "riscv_zero_" UNSPECV_ZERO)] "TARGET_ZICBOZ" "cbo.zero\t%a0" + [(set_attr "type" "cbo")] ) (define_insn "prefetch" @@ -3375,7 +3426,8 @@ (define_insn "prefetch" case 1: return "prefetch.w\t%a0"; default: gcc_unreachable (); } -}) +} + [(set_attr "type" "cbo")]) (define_insn "riscv_prefetchi_" [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r") @@ -3383,7 +3435,7 @@ (define_insn "riscv_prefetchi_" UNSPECV_PREI)] "TARGET_ZICBOP" "prefetch.i\t%a0" -) + [(set_attr "type" "cbo")]) (define_expand "extv" [(set (match_operand:GPR 0 "register_operand" "=r")