From patchwork Wed Aug 30 06:44:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 1827586 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=RA6MTEGl; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RbFDf2FBGz1yfX for ; Wed, 30 Aug 2023 16:45:53 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 65BC93858426 for ; Wed, 30 Aug 2023 06:45:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 65BC93858426 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1693377951; bh=WlFUf++6HXAkeM6U9FIZOc5BhNfpLbcor4dYg8I/Alo=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=RA6MTEGl+8LKgy8lzyFoCoL7ekTdEVGrvs0dT7MXkaB5GVzE6SOuhTNIa59hB7VgZ n3DheMrKhjjwK0hlO72bvGeMe4g/jWPdfHJtYV/iRkh/1wqx6hib88d9vYOLoLXMz4 G+QbY4RRTc14KvVoD/R5LLwwb88Zd9WWfDVSVT5s= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 3D64D3858D35 for ; Wed, 30 Aug 2023 06:45:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3D64D3858D35 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 1FB5C300089; Wed, 30 Aug 2023 06:45:19 +0000 (UTC) To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Jeff Law Cc: gcc-patches@gcc.gnu.org Subject: [RFC PATCH] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support Date: Wed, 30 Aug 2023 06:44:12 +0000 Message-ID: <2adcf40a405ec562076e5cdbc185ff3b7ddd48da.1693377796.git.research_trasio@irq.a4lg.com> Mime-Version: 1.0 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, LIKELY_SPAM_BODY, SPF_HELO_NONE, SPF_PASS, TXREP, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Gcc-patches From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Tsukasa OI 'XVentanaCondOps' is a vendor extension from Ventana Micro Systems containing two instructions for conditional move and will be supported on their Veyron V1 CPU. And most notably (for historical reasons), 'XVentanaCondOps' and the standard 'Zicond' extension are functionally equivalent (only encodings and instruction names are different). * czero.eqz == vt.maskc * czero.nez == vt.maskcn This commit adds support for the 'XVentanaCondOps' extension by extending 'Zicond' extension support. With this, we can now reuse the optimization using the 'Zicond' extension for the 'XVentanaCondOps' extension. The specification for the 'XVentanaCondOps' extension is based on: gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_flag_table): Parse 'XVentanaCondOps' extension. * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New. (TARGET_XVENTANACONDOPS): Ditto. (TARGET_ZICOND_LIKE): New to represent targets with conditional moves like 'Zicond'. It includes RV64 + 'XVentanaCondOps'. * config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND with TARGET_ZICOND_LIKE. (riscv_expand_conditional_move): Ditto. * config/riscv/riscv.md (movcc): Replace TARGET_ZICOND with TARGET_ZICOND_LIKE. * config/riscv/riscv.opt: Add new riscv_xventana_subext. * config/riscv/zicond.md: Modify description. (eqz_ventana): New to match corresponding czero instructions. (nez_ventana): Ditto. (*czero..): Emit a 'XVentanaCondOps' instruction if 'Zicond' is not available but 'XVentanaCondOps' + RV64 is. (*czero..): Ditto. (*czero.eqz..opt1): Ditto. (*czero.nez..opt2): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test, modified from zicond-primitiveSemantics.c. * gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New test to make sure that XVentanaCondOps instructions are disabled on RV32. * gcc.target/riscv/xventanacondops-xor-01.c: New test, modified from zicond-xor-01.c. --- gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/riscv-opts.h | 6 +++ gcc/config/riscv/riscv.cc | 4 +- gcc/config/riscv/riscv.md | 2 +- gcc/config/riscv/riscv.opt | 3 ++ gcc/config/riscv/zicond.md | 53 +++++++++++++++---- .../xventanacondops-primitiveSemantics-rv32.c | 45 ++++++++++++++++ .../xventanacondops-primitiveSemantics.c | 48 +++++++++++++++++ .../gcc.target/riscv/xventanacondops-xor-01.c | 14 +++++ 9 files changed, 163 insertions(+), 14 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c base-commit: a248e1cc860821b96a42be96478257c4964a7c2a diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index f142212f2edc..9a0a68fe5db3 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -1493,6 +1493,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR}, {"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC}, + {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS}, + {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 5ed69abd214d..a4fb0a0a5946 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -319,6 +319,12 @@ enum riscv_entity #define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0) #define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0) +#define MASK_XVENTANACONDOPS (1 << 0) + +#define TARGET_XVENTANACONDOPS ((riscv_xventana_subext & MASK_XVENTANACONDOPS) != 0) + +#define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT)) + /* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode is the highest priority choice and should not conflict with VLS modes. */ #define TARGET_VECTOR_VLS \ diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 2b39a6167442..a3285985e43f 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2725,7 +2725,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN *total = COSTS_N_INSNS (1); return true; } - else if (TARGET_ZICOND + else if (TARGET_ZICOND_LIKE && outer_code == SET && ((GET_CODE (XEXP (x, 1)) == REG && XEXP (x, 2) == CONST0_RTX (GET_MODE (XEXP (x, 1)))) @@ -3822,7 +3822,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) cond, cons, alt))); return true; } - else if (TARGET_ZICOND + else if (TARGET_ZICOND_LIKE && GET_MODE_CLASS (mode) == MODE_INT) { /* The comparison must be comparing WORD_MODE objects. We must diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 0127b9e5abbd..0f61199f1747 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2577,7 +2577,7 @@ (if_then_else:GPR (match_operand 1 "comparison_operator") (match_operand:GPR 2 "sfb_alu_operand") (match_operand:GPR 3 "sfb_alu_operand")))] - "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND" + "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND_LIKE" { if (riscv_expand_conditional_move (operands[0], operands[1], operands[2], operands[3])) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index d2407c3c5021..a3bb3ad3089d 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -257,6 +257,9 @@ int riscv_ztso_subext TargetVariable int riscv_xthead_subext +TargetVariable +int riscv_xventana_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option): diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md index 4619220ef8ac..9c2f470668ac 100644 --- a/gcc/config/riscv/zicond.md +++ b/gcc/config/riscv/zicond.md @@ -1,4 +1,5 @@ -;; Machine description for the RISC-V Zicond extension +;; Machine description for the RISC-V Zicond extension and functionally- +;; equivalent XVentanaCondOps vendor extension ;; Copyright (C) 2022-23 Free Software Foundation, Inc. ;; This file is part of GCC. @@ -20,6 +21,8 @@ (define_code_iterator eq_or_ne [eq ne]) (define_code_attr eqz [(eq "nez") (ne "eqz")]) (define_code_attr nez [(eq "eqz") (ne "nez")]) +(define_code_attr eqz_ventana [(eq "maskcn") (ne "maskc")]) +(define_code_attr nez_ventana [(eq "maskc") (ne "maskcn")]) ;; Zicond (define_insn "*czero.." @@ -28,8 +31,15 @@ (const_int 0)) (match_operand:GPR 2 "register_operand" "r") (const_int 0)))] - "TARGET_ZICOND" - "czero.\t%0,%2,%1" + "TARGET_ZICOND_LIKE" + { + if (TARGET_ZICOND) + return "czero.\t%0,%2,%1"; + else if (TARGET_XVENTANACONDOPS && TARGET_64BIT) + return "vt.\t%0,%2,%1"; + else + gcc_unreachable (); + } ) (define_insn "*czero.." @@ -38,8 +48,15 @@ (const_int 0)) (const_int 0) (match_operand:GPR 2 "register_operand" "r")))] - "TARGET_ZICOND" - "czero.\t%0,%2,%1" + "TARGET_ZICOND_LIKE" + { + if (TARGET_ZICOND) + return "czero.\t%0,%2,%1"; + else if (TARGET_XVENTANACONDOPS && TARGET_64BIT) + return "vt.\t%0,%2,%1"; + else + gcc_unreachable (); + } ) ;; Special optimization under eq/ne in primitive semantics @@ -49,8 +66,15 @@ (const_int 0)) (match_operand:GPR 2 "register_operand" "1") (match_operand:GPR 3 "register_operand" "r")))] - "TARGET_ZICOND && rtx_equal_p (operands[1], operands[2])" - "czero.eqz\t%0,%3,%1" + "TARGET_ZICOND_LIKE && rtx_equal_p (operands[1], operands[2])" + { + if (TARGET_ZICOND) + return "czero.eqz\t%0,%3,%1"; + else if (TARGET_XVENTANACONDOPS && TARGET_64BIT) + return "vt.maskc\t%0,%3,%1"; + else + gcc_unreachable (); + } ) (define_insn "*czero.nez..opt2" @@ -59,8 +83,15 @@ (const_int 0)) (match_operand:GPR 2 "register_operand" "r") (match_operand:GPR 3 "register_operand" "1")))] - "TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])" - "czero.nez\t%0,%2,%1" + "TARGET_ZICOND_LIKE && rtx_equal_p (operands[1], operands[3])" + { + if (TARGET_ZICOND) + return "czero.nez\t%0,%2,%1"; + else if (TARGET_XVENTANACONDOPS && TARGET_64BIT) + return "vt.maskcn\t%0,%2,%1"; + else + gcc_unreachable (); + } ) ;; Combine creates this form in some cases (particularly the coremark @@ -72,7 +103,7 @@ (match_operand 2 "immediate_operand")) (match_operand:X 3 "register_operand"))) (clobber (match_operand:X 4 "register_operand"))] - "TARGET_ZICOND && TARGET_ZBS" + "TARGET_ZICOND_LIKE && TARGET_ZBS" [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) (set (match_dup 0) (if_then_else:X (eq:X (match_dup 4) (const_int 0)) (const_int 0) @@ -85,7 +116,7 @@ (match_operand 2 "immediate_operand")) (match_operand:X 3 "register_operand"))) (clobber (match_operand:X 4 "register_operand"))] - "TARGET_ZICOND && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)" + "TARGET_ZICOND_LIKE && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)" [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2))) (set (match_dup 0) (if_then_else:X (eq:X (match_dup 4) (const_int 0)) (const_int 0) diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c new file mode 100644 index 000000000000..992f1425c54f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xventanacondops -mabi=ilp32d" } */ + +long primitiveSemantics_00(long a, long b) { return a == 0 ? 0 : b; } + +long primitiveSemantics_01(long a, long b) { return a != 0 ? 0 : b; } + +long primitiveSemantics_02(long a, long b) { return a == 0 ? b : 0; } + +long primitiveSemantics_03(long a, long b) { return a != 0 ? b : 0; } + +long primitiveSemantics_04(long a, long b) { + if (a) + b = 0; + return b; +} + +long primitiveSemantics_05(long a, long b) { + if (!a) + b = 0; + return b; +} + +int primitiveSemantics_06(int a, int b) { return a == 0 ? 0 : b; } + +int primitiveSemantics_07(int a, int b) { return a != 0 ? 0 : b; } + +int primitiveSemantics_08(int a, int b) { return a == 0 ? b : 0; } + +int primitiveSemantics_09(int a, int b) { return a != 0 ? b : 0; } + +int primitiveSemantics_10(int a, int b) { + if (a) + b = 0; + return b; +} + +int primitiveSemantics_11(int a, int b) { + if (!a) + b = 0; + return b; +} + +/* { dg-final { scan-assembler-not "vt\\.maskc\t" } } */ +/* { dg-final { scan-assembler-not "vt\\.maskcn\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c new file mode 100644 index 000000000000..04947de6156b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c @@ -0,0 +1,48 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Og"} } */ + +long primitiveSemantics_00(long a, long b) { return a == 0 ? 0 : b; } + +long primitiveSemantics_01(long a, long b) { return a != 0 ? 0 : b; } + +long primitiveSemantics_02(long a, long b) { return a == 0 ? b : 0; } + +long primitiveSemantics_03(long a, long b) { return a != 0 ? b : 0; } + +long primitiveSemantics_04(long a, long b) { + if (a) + b = 0; + return b; +} + +long primitiveSemantics_05(long a, long b) { + if (!a) + b = 0; + return b; +} + +int primitiveSemantics_06(int a, int b) { return a == 0 ? 0 : b; } + +int primitiveSemantics_07(int a, int b) { return a != 0 ? 0 : b; } + +int primitiveSemantics_08(int a, int b) { return a == 0 ? b : 0; } + +int primitiveSemantics_09(int a, int b) { return a != 0 ? b : 0; } + +int primitiveSemantics_10(int a, int b) { + if (a) + b = 0; + return b; +} + +int primitiveSemantics_11(int a, int b) { + if (!a) + b = 0; + return b; +} + +/* { dg-final { scan-assembler-times "vt\\.maskc\t" 6 } } */ +/* { dg-final { scan-assembler-times "vt\\.maskcn\t" 6 } } */ +/* { dg-final { scan-assembler-not "beq" } } */ +/* { dg-final { scan-assembler-not "bne" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c new file mode 100644 index 000000000000..c2f0dc041cb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long xor1(long crc, long poly) +{ + if (crc & 1) + crc ^= poly; + + return crc; +} + +/* { dg-final { scan-assembler-times "vt\\.maskc\t" 1 } } */ +/* { dg-final { scan-assembler-times "xor\t" 1 } } */