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Fri, 25 Aug 2023 06:44:50 +0000 Received: from smtpav02.fra02v.mail.ibm.com (smtpav02.fra02v.mail.ibm.com [10.20.54.101]) by smtprelay01.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 37P6ilA222086146 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 25 Aug 2023 06:44:48 GMT Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D179820043; Fri, 25 Aug 2023 06:44:47 +0000 (GMT) Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0019820040; Fri, 25 Aug 2023 06:44:45 +0000 (GMT) Received: from [9.200.63.168] (unknown [9.200.63.168]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 25 Aug 2023 06:44:45 +0000 (GMT) Message-ID: Date: Fri, 25 Aug 2023 14:44:45 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.14.0 Content-Language: en-US To: gcc-patches Cc: Segher Boessenkool , David , "Kewen.Lin" , Peter Bergner Subject: [PATCH-2, rs6000] Implement 32bit inline lrint [PR88558] X-TM-AS-GCONF: 00 X-Proofpoint-GUID: -QzSFMa3r0ps_YrcsujSIXBN6zxsjrad X-Proofpoint-ORIG-GUID: 4wJjRu8JA2L29QhtBKlC3paffgwt4ep7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-25_04,2023-08-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 mlxscore=0 adultscore=0 priorityscore=1501 malwarescore=0 phishscore=0 clxscore=1015 mlxlogscore=675 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308250056 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: HAO CHEN GUI via Gcc-patches From: HAO CHEN GUI Reply-To: HAO CHEN GUI Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, This patch implements 32bit inline lrint by "fctiw". It depends on the patch1 to do SImode move from FP register on P7. Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. Thanks Gui Haochen ChangeLog rs6000: support 32bit inline lrint gcc/ PR target/88558 * config/rs6000/rs6000.md (lrintdi2): Remove TARGET_FPRND from insn condition. (lrintsi2): New insn pattern for 32bit lrint. gcc/testsuite/ PR target/106769 * gcc.target/powerpc/pr88558.h: New. * gcc.target/powerpc/pr88558-p7.c: New. * gcc.target/powerpc/pr88558-p8v.c: New. patch.diff diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index fd263e8dfe3..b36304de8c6 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -6655,10 +6655,18 @@ (define_insn "lrintdi2" [(set (match_operand:DI 0 "gpc_reg_operand" "=d") (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "")] UNSPEC_FCTID))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT" "fctid %0,%1" [(set_attr "type" "fp")]) +(define_insn "lrintsi2" + [(set (match_operand:SI 0 "gpc_reg_operand" "=d") + (unspec:SI [(match_operand:SFDF 1 "gpc_reg_operand" "")] + UNSPEC_FCTIW))] + "TARGET_HARD_FLOAT && TARGET_POPCNTD" + "fctiw %0,%1" + [(set_attr "type" "fp")]) + (define_insn "btrunc2" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] diff --git a/gcc/testsuite/gcc.target/powerpc/pr88558-p7.c b/gcc/testsuite/gcc.target/powerpc/pr88558-p7.c new file mode 100644 index 00000000000..6437c55fa61 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr88558-p7.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-math-errno -mdejagnu-cpu=power7" } */ + +#include "pr88558.h" + +/* { dg-final { scan-assembler-times {\mfctid\M} 2 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\mfctid\M} 1 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mfctiw\M} 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\mfctiw\M} 2 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mstfiwx\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr88558-p8v.c b/gcc/testsuite/gcc.target/powerpc/pr88558-p8v.c new file mode 100644 index 00000000000..fd22123ffb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr88558-p8v.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-O2 -fno-math-errno -mdejagnu-cpu=power8" } */ + +long int foo (double a) +{ + return __builtin_lrint (a); +} + +long long bar (double a) +{ + return __builtin_llrint (a); +} + +int baz (double a) +{ + return __builtin_irint (a); +} + +/* { dg-final { scan-assembler-times {\mfctid\M} 2 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\mfctid\M} 1 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mfctiw\M} 1 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {\mfctiw\M} 2 { target ilp32 } } } */ +/* { dg-final { scan-assembler-times {\mmfvsrwz\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr88558.h b/gcc/testsuite/gcc.target/powerpc/pr88558.h new file mode 100644 index 00000000000..0cc0c68dd4e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr88558.h @@ -0,0 +1,14 @@ +long int foo (double a) +{ + return __builtin_lrint (a); +} + +long long bar (double a) +{ + return __builtin_llrint (a); +} + +int baz (double a) +{ + return __builtin_irint (a); +}