From patchwork Fri Aug 25 04:43:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Hongtao" X-Patchwork-Id: 1825775 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=kaSJFoYE; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RX6ms6NKhz1yg5 for ; Fri, 25 Aug 2023 14:44:28 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8E9E43858412 for ; Fri, 25 Aug 2023 04:44:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8E9E43858412 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1692938665; bh=RwybiD3xAl/7ScTkEZHyb73YsfV6p9KFWAR2/aN7ags=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=kaSJFoYEbifQzv70+LWcBM99/A1PHslyvSEjAHEkRGUmUq9LrhQ5L+Hwb49cnfxXK anCWHxDEGFSatzK6+H7SyAv7fbR95Y+duY9mYdO2SrpSKMR8zDIZDBHH7IBIbqL0pS arVBGZZolYj9yxraz0iYbXqS0x3X7jwsdUO6ntHo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id 53EF93858C53 for ; Fri, 25 Aug 2023 04:44:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 53EF93858C53 X-IronPort-AV: E=McAfee;i="6600,9927,10812"; a="354959409" X-IronPort-AV: E=Sophos;i="6.02,195,1688454000"; d="scan'208";a="354959409" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Aug 2023 21:44:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10812"; a="687158859" X-IronPort-AV: E=Sophos;i="6.02,195,1688454000"; d="scan'208";a="687158859" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga003.jf.intel.com with ESMTP; 24 Aug 2023 21:43:58 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 56E5410079A7; Fri, 25 Aug 2023 12:43:57 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com Subject: [PATCH] Use vmaskmov{ps, pd} for VI48_128_256 when TARGET_AVX2 is not available. Date: Fri, 25 Aug 2023 12:43:57 +0800 Message-Id: <20230825044357.1669621-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: "Liu, Hongtao" Reply-To: liuhongt Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" vpmaskmov{d,q} is available for TARGET_AVX2, vmaskmov{ps,ps} is available for TARGET_AVX, w/o TARGET_AVX2, we can use vmaskmov{ps,pd} for VI48_128_256 Bootstrapped and regtested on x86_64-pc-linux{-m32,}. Ready push to trunk. gcc/ChangeLog: PR target/111119 * config/i386/sse.md (V48_AVX2): Rename to .. (V48_128_256): .. this. (ssefltmodesuffix): Extend to V4SF/V8SF/V2DF/V4DF. (_maskload): Change V48_AVX2 to V48_128_256, also generate vmaskmov{ps,pd} for integral modes when TARGET_AVX2 is not available. (_maskstore): Ditto. (maskload): Change V48_AVX2 to V48_128_256. (maskstore): Ditto. --- gcc/config/i386/sse.md | 48 ++++++++++++++++++++++++++---------------- 1 file changed, 30 insertions(+), 18 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 59a0eb1c63f..414a807aa6c 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -700,11 +700,12 @@ (define_mode_iterator VI12_AVX_AVX512F [ (V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX") V8HI]) -(define_mode_iterator V48_AVX2 +(define_mode_iterator V48_128_256 [V4SF V2DF + V4DI V2DI V8SF V4DF - (V4SI "TARGET_AVX2") (V2DI "TARGET_AVX2") - (V8SI "TARGET_AVX2") (V4DI "TARGET_AVX2")]) + V8SI V4SI]) + (define_mode_iterator VF4_128_8_256 [V4DF V4SF]) @@ -22300,7 +22301,8 @@ (define_insn_and_split "*_blendv_lt" (set_attr "mode" "")]) (define_mode_attr ssefltmodesuffix - [(V2DI "pd") (V4DI "pd") (V4SI "ps") (V8SI "ps")]) + [(V2DI "pd") (V4DI "pd") (V4SI "ps") (V8SI "ps") + (V2DF "pd") (V4DF "pd") (V4SF "ps") (V8SF "ps")]) (define_mode_attr ssefltvecmode [(V2DI "V2DF") (V4DI "V4DF") (V4SI "V4SF") (V8SI "V8SF")]) @@ -27411,13 +27413,18 @@ (define_insn "vec_set_hi_v32qi" (set_attr "mode" "OI")]) (define_insn "_maskload" - [(set (match_operand:V48_AVX2 0 "register_operand" "=x") - (unspec:V48_AVX2 + [(set (match_operand:V48_128_256 0 "register_operand" "=x") + (unspec:V48_128_256 [(match_operand: 2 "register_operand" "x") - (match_operand:V48_AVX2 1 "memory_operand" "m")] + (match_operand:V48_128_256 1 "memory_operand" "m")] UNSPEC_MASKMOV))] "TARGET_AVX" - "vmaskmov\t{%1, %2, %0|%0, %2, %1}" +{ + if (TARGET_AVX2) + return "vmaskmov\t{%1, %2, %0|%0, %2, %1}"; + else + return "vmaskmov\t{%1, %2, %0|%0, %2, %1}"; +} [(set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "prefix" "vex") @@ -27425,14 +27432,19 @@ (define_insn "_maskload" (set_attr "mode" "")]) (define_insn "_maskstore" - [(set (match_operand:V48_AVX2 0 "memory_operand" "+m") - (unspec:V48_AVX2 + [(set (match_operand:V48_128_256 0 "memory_operand" "+m") + (unspec:V48_128_256 [(match_operand: 1 "register_operand" "x") - (match_operand:V48_AVX2 2 "register_operand" "x") + (match_operand:V48_128_256 2 "register_operand" "x") (match_dup 0)] UNSPEC_MASKMOV))] "TARGET_AVX" - "vmaskmov\t{%2, %1, %0|%0, %1, %2}" +{ + if (TARGET_AVX2) + return "vmaskmov\t{%2, %1, %0|%0, %1, %2}"; + else + return "vmaskmov\t{%2, %1, %0|%0, %1, %2}"; +} [(set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "prefix" "vex") @@ -27440,10 +27452,10 @@ (define_insn "_maskstore" (set_attr "mode" "")]) (define_expand "maskload" - [(set (match_operand:V48_AVX2 0 "register_operand") - (unspec:V48_AVX2 + [(set (match_operand:V48_128_256 0 "register_operand") + (unspec:V48_128_256 [(match_operand: 2 "register_operand") - (match_operand:V48_AVX2 1 "memory_operand")] + (match_operand:V48_128_256 1 "memory_operand")] UNSPEC_MASKMOV))] "TARGET_AVX") @@ -27468,10 +27480,10 @@ (define_expand "maskload" "TARGET_AVX512BW") (define_expand "maskstore" - [(set (match_operand:V48_AVX2 0 "memory_operand") - (unspec:V48_AVX2 + [(set (match_operand:V48_128_256 0 "memory_operand") + (unspec:V48_128_256 [(match_operand: 2 "register_operand") - (match_operand:V48_AVX2 1 "register_operand") + (match_operand:V48_128_256 1 "register_operand") (match_dup 0)] UNSPEC_MASKMOV))] "TARGET_AVX")