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Thu, 24 Aug 2023 14:20:12 -0700 (PDT) Received: from ewlu.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id q9-20020a17090a68c900b0026b3773043dsm163694pjj.22.2023.08.24.14.20.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Aug 2023 14:20:12 -0700 (PDT) From: Edwin Lu To: gcc-patches@gcc.gnu.org Cc: gnu-toolchain@rivosinc.com, Edwin Lu Subject: [PATCH V2] RISC-V: Add Types to Un-Typed Sync Instructions: Date: Thu, 24 Aug 2023 14:19:05 -0700 Message-ID: <20230824211957.671151-1-ewlu@rivosinc.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Related Discussion: https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5eb2@gmail.com/ This patch updates the sync instructions to ensure that no insn is left without a type attribute. Updates a total of 6 insns to have type "atomic" Tested for regressions using rv32/64 multilib with newlib/linux. gcc/Changelog: * config/riscv/sync-rvwmo.md: updated types to "multi" or "atomic" based on number of assembly lines generated * config/riscv/sync-ztso.md: likewise * config/riscv/sync.md: likewise Signed-off-by: Edwin Lu --- Changes in V2: - Update insns that were typed "atomic" to "multi" if insn can generate multiple lines of assembly following https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628055.html --- gcc/config/riscv/sync-rvwmo.md | 7 ++++--- gcc/config/riscv/sync-ztso.md | 7 ++++--- gcc/config/riscv/sync.md | 14 +++++++++----- 3 files changed, 17 insertions(+), 11 deletions(-) diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md index 1fc7cf16b5b..cb641ea9ec3 100644 --- a/gcc/config/riscv/sync-rvwmo.md +++ b/gcc/config/riscv/sync-rvwmo.md @@ -41,7 +41,8 @@ (define_insn "mem_thread_fence_rvwmo" else gcc_unreachable (); } - [(set (attr "length") (const_int 4))]) + [(set_attr "type" "atomic") + (set (attr "length") (const_int 4))]) ;; Atomic memory operations. @@ -66,7 +67,7 @@ (define_insn "atomic_load_rvwmo" else return "l\t%0,%1"; } - [(set_attr "type" "atomic") + [(set_attr "type" "multi") (set (attr "length") (const_int 12))]) ;; Implement atomic stores with conservative fences. @@ -92,5 +93,5 @@ (define_insn "atomic_store_rvwmo" else return "s\t%z1,%0"; } - [(set_attr "type" "atomic") + [(set_attr "type" "multi") (set (attr "length") (const_int 12))]) diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md index ed94471b96b..7bb15b7ab8c 100644 --- a/gcc/config/riscv/sync-ztso.md +++ b/gcc/config/riscv/sync-ztso.md @@ -35,7 +35,8 @@ (define_insn "mem_thread_fence_ztso" else gcc_unreachable (); } - [(set (attr "length") (const_int 4))]) + [(set_attr "type" "atomic") + (set (attr "length") (const_int 4))]) ;; Atomic memory operations. @@ -56,7 +57,7 @@ (define_insn "atomic_load_ztso" else return "l\t%0,%1"; } - [(set_attr "type" "atomic") + [(set_attr "type" "multi") (set (attr "length") (const_int 12))]) (define_insn "atomic_store_ztso" @@ -76,5 +77,5 @@ (define_insn "atomic_store_ztso" else return "s\t%z1,%0"; } - [(set_attr "type" "atomic") + [(set_attr "type" "multi") (set (attr "length") (const_int 8))]) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 2f85951508f..6ff3493b5ce 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -136,7 +136,8 @@ (define_insn "subword_atomic_fetch_strong_" "sc.w%J3\t%6, %7, %1\;" "bnez\t%6, 1b"; } - [(set (attr "length") (const_int 28))]) + [(set_attr "type" "multi") + (set (attr "length") (const_int 28))]) (define_expand "atomic_fetch_nand" [(match_operand:SHORT 0 "register_operand") ;; old value at mem @@ -203,7 +204,8 @@ (define_insn "subword_atomic_fetch_strong_nand" "sc.w%J3\t%6, %7, %1\;" "bnez\t%6, 1b"; } - [(set (attr "length") (const_int 32))]) + [(set_attr "type" "multi") + (set (attr "length") (const_int 32))]) (define_expand "atomic_fetch_" [(match_operand:SHORT 0 "register_operand") ;; old value at mem @@ -310,7 +312,8 @@ (define_insn "subword_atomic_exchange_strong" "sc.w%J3\t%5, %5, %1\;" "bnez\t%5, 1b"; } - [(set (attr "length") (const_int 20))]) + [(set_attr "type" "multi") + (set (attr "length") (const_int 20))]) (define_insn "atomic_cas_value_strong" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -336,7 +339,7 @@ (define_insn "atomic_cas_value_strong" "bnez\t%6,1b\;" "1:"; } - [(set_attr "type" "atomic") + [(set_attr "type" "multi") (set (attr "length") (const_int 16))]) (define_expand "atomic_compare_and_swap" @@ -497,7 +500,8 @@ (define_insn "subword_atomic_cas_strong" "bnez\t%7, 1b\;" "1:"; } - [(set (attr "length") (const_int 28))]) + [(set_attr "type" "multi") + (set (attr "length") (const_int 28))]) (define_expand "atomic_test_and_set" [(match_operand:QI 0 "register_operand" "") ;; bool output