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Content preview: For parameter page read upper layer is passing len as 256 bytes and if we try to configure 256 bytes size in read loaction register then subsequent bam transaction is getting timed out for 4K nand dev [...] Content analysis details: (0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [205.220.168.131 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 SPF_NONE SPF: sender does not publish an SPF Record 0.2 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org For parameter page read upper layer is passing len as 256 bytes and if we try to configure 256 bytes size in read loaction register then subsequent bam transaction is getting timed out for 4K nand devices. So update this length as one step size if its less than NANDC_STEP_SIZE. Signed-off-by: Sricharan Ramabadhran Signed-off-by: Md Sadre Alam --- drivers/mtd/nand/raw/qcom_nandc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index d4ba0d04c970..413e214c8e87 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2885,6 +2885,9 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_ op_id = q_op.data_instr_idx; len = nand_subop_get_data_len(subop, op_id); + if (len < NANDC_STEP_SIZE) + len = NANDC_STEP_SIZE; + nandc_set_read_loc(chip, 0, 0, 0, len, 1); if (!nandc->props->qpic_v2) { From patchwork Fri Aug 18 14:51:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 1822975 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; 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Fri, 18 Aug 2023 14:51:08 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 37IEp5ej000308; Fri, 18 Aug 2023 14:51:05 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3se35mqdxy-1; Fri, 18 Aug 2023 14:51:05 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 37IEp4Qq000300; Fri, 18 Aug 2023 14:51:05 GMT Received: from mdalam-linux.qualcomm.com (mdalam-linux.qualcomm.com [10.201.2.71]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 37IEp4UO032767; Fri, 18 Aug 2023 14:51:04 +0000 Received: by mdalam-linux.qualcomm.com (Postfix, from userid 466583) id 1F0C31200077; Fri, 18 Aug 2023 20:21:04 +0530 (IST) From: Md Sadre Alam To: mani@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: quic_mdalam@quicinc.com, quic_srichara@quicinc.com Subject: [PATCH 2/3] mtd: rawnand: qcom: Clear buf_count and buf_start in raw read Date: Fri, 18 Aug 2023 20:21:00 +0530 Message-Id: <20230818145101.23825-3-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230818145101.23825-1-quic_mdalam@quicinc.com> References: <20230818145101.23825-1-quic_mdalam@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: XiZaebA4NENsixwCBFJIeIMP7-4RAVTQ X-Proofpoint-ORIG-GUID: XiZaebA4NENsixwCBFJIeIMP7-4RAVTQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-18_18,2023-08-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 adultscore=0 spamscore=0 impostorscore=0 suspectscore=0 bulkscore=0 malwarescore=0 clxscore=1015 mlxscore=0 priorityscore=1501 mlxlogscore=882 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308180135 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230818_075113_587564_97CC0B22 X-CRM114-Status: GOOD ( 13.88 ) X-Spam-Score: 0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Initialize buf_count and buf_start to 0 before starting the raw read. If we will not initialize then read staus will get updated with wrong value and we will see failure for even successful raw read t [...] Content analysis details: (0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [205.220.168.131 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 SPF_NONE SPF: sender does not publish an SPF Record 0.2 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Initialize buf_count and buf_start to 0 before starting the raw read. If we will not initialize then read staus will get updated with wrong value and we will see failure for even successful raw read transaction. Signed-off-by: Sricharan Ramabadhran Signed-off-by: Md Sadre Alam --- drivers/mtd/nand/raw/qcom_nandc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 413e214c8e87..73dd1b4e4e31 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -1471,6 +1471,9 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip, int raw_cw = cw; nand_read_page_op(chip, page, 0, NULL, 0); + nandc->buf_count = 0; + nandc->buf_start = 0; + clear_read_regs(nandc); host->use_ecc = false; if (nandc->props->qpic_v2) From patchwork Fri Aug 18 14:51:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 1822977 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=hKUK7g3r; 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Fri, 18 Aug 2023 14:51:06 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 37IEp4Qs000300; Fri, 18 Aug 2023 14:51:05 GMT Received: from mdalam-linux.qualcomm.com (mdalam-linux.qualcomm.com [10.201.2.71]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 37IEp4UQ032767; Fri, 18 Aug 2023 14:51:05 +0000 Received: by mdalam-linux.qualcomm.com (Postfix, from userid 466583) id ECC7512010CE; Fri, 18 Aug 2023 20:21:04 +0530 (IST) From: Md Sadre Alam To: mani@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: quic_mdalam@quicinc.com, quic_srichara@quicinc.com Subject: [PATCH 3/3] mtd: rawnand: qcom: Add read/read_start ops in exec_op path Date: Fri, 18 Aug 2023 20:21:01 +0530 Message-Id: <20230818145101.23825-4-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230818145101.23825-1-quic_mdalam@quicinc.com> References: <20230818145101.23825-1-quic_mdalam@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ghE0kJoYG9k2M4PbFHW5ZD9abiubilfk X-Proofpoint-ORIG-GUID: ghE0kJoYG9k2M4PbFHW5ZD9abiubilfk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-18_18,2023-08-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 phishscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 adultscore=0 clxscore=1015 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308180135 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230818_075113_951085_03BABB15 X-CRM114-Status: GOOD ( 19.66 ) X-Spam-Score: 0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Sricharan Ramabadhran READ/READ_START opcodes are not set in exec_op path. Fixing that here. While there, Steps to program the controller is common for erase/reset/read/program page. So use a common pattern and pull them under one function. Content analysis details: (0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [205.220.168.131 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 SPF_NONE SPF: sender does not publish an SPF Record 0.2 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Sricharan Ramabadhran READ/READ_START opcodes are not set in exec_op path. Fixing that here. While there, Steps to program the controller is common for erase/reset/read/program page. So use a common pattern and pull them under one function. Signed-off-by: Md Sadre Alam Signed-off-by: Sricharan Ramabadhran --- drivers/mtd/nand/raw/qcom_nandc.c | 93 ++++++++++++------------------- 1 file changed, 35 insertions(+), 58 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 73dd1b4e4e31..370a779610e2 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2541,9 +2541,11 @@ static int qcom_nand_attach_chip(struct nand_chip *chip) return 0; } -static int qcom_op_cmd_mapping(struct qcom_nand_controller *nandc, u8 opcode, +static int qcom_op_cmd_mapping(struct nand_chip *chip, u8 opcode, struct qcom_op *q_op) { + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + struct qcom_nand_host *host = to_qcom_nand_host(chip); int cmd; switch (opcode) { @@ -2571,6 +2573,13 @@ static int qcom_op_cmd_mapping(struct qcom_nand_controller *nandc, u8 opcode, q_op->flag = OP_PROGRAM_PAGE; nandc->exec_opwrite = true; break; + case NAND_CMD_READ0: + case NAND_CMD_READSTART: + if (host->use_ecc) + cmd = OP_PAGE_READ_WITH_ECC; + else + cmd = OP_PAGE_READ; + break; default: dev_err(nandc->dev, "Opcode not supported: %u\n", opcode); return -EOPNOTSUPP; @@ -2597,7 +2606,7 @@ static int qcom_parse_instructions(struct nand_chip *chip, switch (instr->type) { case NAND_OP_CMD_INSTR: - ret = qcom_op_cmd_mapping(nandc, instr->ctx.cmd.opcode, q_op); + ret = qcom_op_cmd_mapping(chip, instr->ctx.cmd.opcode, q_op); if (ret < 0) return ret; @@ -2791,13 +2800,25 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub struct qcom_nand_host *host = to_qcom_nand_host(chip); struct qcom_op q_op = {}; int ret; + int instrs = 1; ret = qcom_parse_instructions(chip, subop, &q_op); if (ret) return ret; - if (q_op.flag == OP_PROGRAM_PAGE) + if (q_op.flag == OP_PROGRAM_PAGE) { goto wait_rdy; + } else if (q_op.cmd_reg == OP_BLOCK_ERASE) { + q_op.cmd_reg |= PAGE_ACC | LAST_PAGE; + nandc_set_reg(chip, NAND_ADDR0, q_op.addr1_reg); + nandc_set_reg(chip, NAND_ADDR1, q_op.addr2_reg); + nandc_set_reg(chip, NAND_DEV0_CFG0, + host->cfg0_raw & ~(7 << CW_PER_PAGE)); + nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw); + instrs = 3; + } else { + return 0; + } nandc->buf_count = 0; nandc->buf_start = 0; @@ -2809,9 +2830,12 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); nandc_set_reg(chip, NAND_EXEC_CMD, 1); - write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); - write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL); + (q_op.cmd_reg == OP_BLOCK_ERASE) ? write_reg_dma(nandc, NAND_DEV0_CFG0, + 2, NAND_BAM_NEXT_SGL) : read_reg_dma(nandc, + NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); ret = submit_descs(nandc); @@ -2928,56 +2952,7 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_ return ret; } -static int qcom_erase_cmd_type_exec(struct nand_chip *chip, const struct nand_subop *subop) -{ - struct qcom_nand_host *host = to_qcom_nand_host(chip); - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - struct qcom_op q_op = {}; - int ret; - - ret = qcom_parse_instructions(chip, subop, &q_op); - if (ret) - return ret; - - q_op.cmd_reg |= PAGE_ACC | LAST_PAGE; - - nandc->buf_count = 0; - nandc->buf_start = 0; - host->use_ecc = false; - clear_read_regs(nandc); - clear_bam_transaction(nandc); - - nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); - nandc_set_reg(chip, NAND_ADDR0, q_op.addr1_reg); - nandc_set_reg(chip, NAND_ADDR1, q_op.addr2_reg); - nandc_set_reg(chip, NAND_DEV0_CFG0, - host->cfg0_raw & ~(7 << CW_PER_PAGE)); - nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw); - nandc_set_reg(chip, NAND_EXEC_CMD, 1); - - write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); - write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); - write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); - - ret = submit_descs(nandc); - if (ret) { - dev_err(nandc->dev, "failure in submitting erase descriptor\n"); - goto err_out; - } - - ret = qcom_wait_rdy_poll(chip, q_op.rdy_timeout_ms); - if (ret) - goto err_out; - -err_out: - return ret; -} - static const struct nand_op_parser qcom_op_parser = NAND_OP_PARSER( - NAND_OP_PARSER_PATTERN( - qcom_misc_cmd_type_exec, - NAND_OP_PARSER_PAT_CMD_ELEM(false), - NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), NAND_OP_PARSER_PATTERN( qcom_read_id_type_exec, NAND_OP_PARSER_PAT_CMD_ELEM(false), @@ -2994,10 +2969,10 @@ static const struct nand_op_parser qcom_op_parser = NAND_OP_PARSER( NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 512)), NAND_OP_PARSER_PATTERN( - qcom_erase_cmd_type_exec, - NAND_OP_PARSER_PAT_CMD_ELEM(false), - NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYCLE), + qcom_misc_cmd_type_exec, NAND_OP_PARSER_PAT_CMD_ELEM(false), + NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYCLE), + NAND_OP_PARSER_PAT_CMD_ELEM(true), NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), ); @@ -3018,7 +2993,9 @@ static int qcom_check_op(struct nand_chip *chip, instr->ctx.cmd.opcode != NAND_CMD_ERASE1 && instr->ctx.cmd.opcode != NAND_CMD_ERASE2 && instr->ctx.cmd.opcode != NAND_CMD_STATUS && - instr->ctx.cmd.opcode != NAND_CMD_PAGEPROG) + instr->ctx.cmd.opcode != NAND_CMD_PAGEPROG && + instr->ctx.cmd.opcode != NAND_CMD_READ0 && + instr->ctx.cmd.opcode != NAND_CMD_READSTART) return -EOPNOTSUPP; break; default: