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Wed, 16 Aug 2023 03:42:52 -0700 (PDT) From: Hsin-Yi Wang To: Tudor Ambarus , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Bjorn Andersson Cc: Pratyush Yadav , Michael Walle , "Miquel Raynal )" , "Richard Weinberger )" , "Vignesh Raghavendra )" , Rob Herring , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, cros-qcom-dts-watchers@chromium.org, Andy Gross , Konrad Dybcio Subject: [PATCH v2,1/2] mtd: spi-nor: giga: gd25lq64c: Disable quad mode according to bus width Date: Wed, 16 Aug 2023 18:38:32 +0800 Message-ID: <20230816104245.2676965-1-hsinyi@chromium.org> X-Mailer: git-send-email 2.41.0.694.ge786442a9b-goog MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230816_034255_303001_2FDC0E64 X-CRM114-Status: GOOD ( 16.44 ) X-Spam-Score: -0.4 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: gd25lq64c has Quad Enable Requirement flag parsed as BFPT_DWORD15_QER_SR2_BIT1_BUGGY in BFPT, even if spi-{rx/tx}-bus-width set as non QUAD, eg. 0, 1, 2... Thus quad_enable will not be NULL and quad e [...] Content analysis details: (-0.4 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:62e listed in] [list.dnswl.org] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.2 DKIMWL_WL_HIGH DKIMwl.org - High trust sender X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org gd25lq64c has Quad Enable Requirement flag parsed as BFPT_DWORD15_QER_SR2_BIT1_BUGGY in BFPT, even if spi-{rx/tx}-bus-width set as non QUAD, eg. 0, 1, 2... Thus quad_enable will not be NULL and quad enable (QE) bit will be set to 1 by default. According to datasheet[1], if QE bit is enabled, WP pin will become IO pin and the system can't use write protection feature, and it's also not recommended to set QE bit to 1[1]. Add a post_bfpt fixup that reads spi-rx-bus-width to remove quad_enable if the width is set to below QUAD mode. [1] https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00012-GD25LQ64C-Rev3.4.pdf page 13 Signed-off-by: Hsin-Yi Wang --- drivers/mtd/spi-nor/gigadevice.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c index d57ddaf1525b3..8ea89e1858f9b 100644 --- a/drivers/mtd/spi-nor/gigadevice.c +++ b/drivers/mtd/spi-nor/gigadevice.c @@ -33,6 +33,31 @@ static const struct spi_nor_fixups gd25q256_fixups = { .post_bfpt = gd25q256_post_bfpt, }; +static int +gd25lq64c_post_bfpt(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, + const struct sfdp_bfpt *bfpt) +{ + struct device_node *np = spi_nor_get_flash_node(nor); + u32 value; + + /* + * Even if spi-{tx,rx}-bus-width is set to DUAL mode, due to the QER + * flag parsed from BFPT is BFPT_DWORD15_QER_SR2_BIT1_BUGGY, so the + * quad_enable will be set and QE bit set to 1. + */ + if (!of_property_read_u32(np, "spi-rx-bus-width", &value)) { + if (value <= 2) + nor->params->quad_enable = NULL; + } + + return 0; +} + +static struct spi_nor_fixups gd25lq64c_fixups = { + .post_bfpt = gd25lq64c_post_bfpt, +}; + static const struct flash_info gigadevice_nor_parts[] = { { "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32) FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) @@ -53,7 +78,8 @@ static const struct flash_info gigadevice_nor_parts[] = { { "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128) FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | - SPI_NOR_QUAD_READ) }, + SPI_NOR_QUAD_READ) + .fixups = &gd25lq64c_fixups }, { "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256) FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | From patchwork Wed Aug 16 10:38:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hsin-Yi Wang X-Patchwork-Id: 1821753 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Some of the SKUs are using gigadevice gd25lq64c flash chip. The chip default enables quad mode, which results in the write protect pin set to IO pin. In mt8183 kukui, we won't use quad enable for all [...] Content analysis details: (-0.4 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:634 listed in] [list.dnswl.org] -0.2 DKIMWL_WL_HIGH DKIMwl.org - High trust sender X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Some of the SKUs are using gigadevice gd25lq64c flash chip. The chip default enables quad mode, which results in the write protect pin set to IO pin. In mt8183 kukui, we won't use quad enable for all SKUs, so apply the property to disable spi nor's quad mode. Signed-off-by: Hsin-Yi Wang --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 6ce16a265e053..ef472b522f2e7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -877,6 +877,7 @@ w25q64dw: flash@0 { compatible = "winbond,w25q64dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <25000000>; + spi-rx-bus-width = <2>; }; };