From patchwork Thu Aug 10 10:32:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Liang X-Patchwork-Id: 1819784 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RM3Cr1g5xz1yYl for ; Thu, 10 Aug 2023 20:32:54 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 46848866C2; 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spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 37AAWXBj080732; Thu, 10 Aug 2023 18:32:33 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from swlinux02 (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 10 Aug 2023 18:32:33 +0800 Date: Thu, 10 Aug 2023 18:32:30 +0800 From: Leo Liang To: CC: , , Subject: [PULL] u-boot-riscv/master Message-ID: MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/2.2.10 (e0e92c31) (2023-03-25) X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 37AAWXBj080732 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Hi Tom, The following changes since commit ec58228830a1f68e8e65099387cf12c5a91c9e72: Merge tag 'x86-pull-20230809' of https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-09 13:17:34 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 47ed15125cccd98e041cdff3b6bbe675a2418ec2: riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE (2023-08-10 10:58:55 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17276 ---------------------------------------------------------------- + Add USB host support on VisionFive2 board + Enable SPI flash support on VisionFive2 board + Enable Random Number Generator in RISC-V QEMU board + Display new SBI extension + Add SPL_ZERO_MEM_BEFORE_USE Kconfig for jh7110 L2 LIM (Loosely-Integrated Memory) ---------------------------------------------------------------- Heinrich Schuchardt (2): riscv: qemu: imply CONFIG_DM_RNG cmd/sbi: display new extensions Minda Chen (4): pci: plda: Get correct ECAM offset in multiple PCIe RC case riscv: dts: starfive: Enable pcie0 dts node riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE configs: riscv: starfive: Add VF2 PCIe USB3 XHCI support Shengyu Qu (4): configs: starfive: Enable environment in SPI flash support riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE arch/riscv/Kconfig | 8 ++++++++ arch/riscv/cpu/jh7110/Kconfig | 2 ++ arch/riscv/cpu/jh7110/spl.c | 25 ------------------------- arch/riscv/cpu/start.S | 12 ++++++++++++ arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 2 +- arch/riscv/include/asm/sbi.h | 2 ++ board/emulation/qemu-riscv/Kconfig | 1 + cmd/riscv/sbi.c | 4 ++++ common/init/board_init.c | 3 +++ configs/starfive_visionfive2_defconfig | 14 ++++++++++++++ drivers/pci/pcie_plda_common.c | 5 +++-- 11 files changed, 50 insertions(+), 28 deletions(-) Best regards, Leo