From patchwork Thu Aug 10 02:25:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 1819667 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=c7UOFs3s; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RLrQZ6QhMz1yYl for ; Thu, 10 Aug 2023 12:26:30 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BD5AC3856DFB for ; Thu, 10 Aug 2023 02:26:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BD5AC3856DFB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691634388; bh=1yXmSPYlAnDkflScl2tv2zqZsGATFp3KcZNmaiLPlZ0=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=c7UOFs3sHgkeBpS+ysdhb5aa+AFavGgOMDaxyOl9WWKwJeDyTjIrZhe5ttWKmT1Ox RzSQJJizCDHNEwvFER2jy/y7gkJwNBhbGU44Ovcer8OfGHyLwPTCvYPcplPy6Ch8Yo BUNWpE/ngD5vrWZtS+2O2aTPZCc/rSU7zeY4bETY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id A68C63858004 for ; Thu, 10 Aug 2023 02:25:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A68C63858004 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 94A37300089; Thu, 10 Aug 2023 02:25:21 +0000 (UTC) To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Jeff Law Cc: gcc-patches@gcc.gnu.org Subject: [RFC PATCH v2 1/2] RISC-V: __builtin_riscv_pause for all environment Date: Thu, 10 Aug 2023 02:25:06 +0000 Message-ID: <22ed79b136f894744e86c1074998593e15c20e58.1691634305.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Gcc-patches From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Tsukasa OI The "pause" RISC-V hint instruction requires the 'Zihintpause' extension (in the assembler). However, GCC emits "pause" unconditionally, making an assembler error while compiling code with __builtin_riscv_pause while the 'Zihintpause' extension disabled. However, the "pause" instruction code (0x0100000f) is a HINT and emitting its instruction code is safe in any environment. This commit implements handling for the 'Zihintpause' extension and emits ".insn 0x0100000f" instead of "pause" only if the extension is disabled (making the diagnostics better). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Implement the 'Zihintpause' extension, version 2.0. (riscv_ext_flag_table) Add 'Zihintpause' handling. * config/riscv/riscv-builtins.cc: Remove availability predicate "always" and add "hint_pause" and "hint_pause_pseudo", corresponding the existence of the 'Zihintpause' extension. (riscv_builtins) Split builtin implementation depending on the existence of the 'Zihintpause' extension. * config/riscv/riscv-opts.h (MASK_ZIHINTPAUSE, TARGET_ZIHINTPAUSE): New. * config/riscv/riscv.md (riscv_pause): Make it only available when the 'Zihintpause' extension is enabled. (riscv_pause_insn) New "pause" implementation when the 'Zihintpause' extension is disabled. gcc/testsuite/ChangeLog: * gcc.target/riscv/builtin_pause.c: Removed. * gcc.target/riscv/zihintpause-1.c: New test when the 'Zihintpause' extension is enabled. * gcc.target/riscv/zihintpause-2.c: Likewise. * gcc.target/riscv/zihintpause-noarch.c: New test when the 'Zihintpause' extension is disabled. --- gcc/common/config/riscv/riscv-common.cc | 2 ++ gcc/config/riscv/riscv-builtins.cc | 6 ++++-- gcc/config/riscv/riscv-opts.h | 2 ++ gcc/config/riscv/riscv.md | 7 ++++++- gcc/testsuite/gcc.target/riscv/builtin_pause.c | 10 ---------- gcc/testsuite/gcc.target/riscv/zihintpause-1.c | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/zihintpause-2.c | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/zihintpause-noarch.c | 12 ++++++++++++ 8 files changed, 48 insertions(+), 13 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/riscv/builtin_pause.c create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause-noarch.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index f25131eab28b..b77fdb909567 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -209,6 +209,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zkt", ISA_SPEC_CLASS_NONE, 1, 0}, {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zihintpause", ISA_SPEC_CLASS_NONE, 2, 0}, {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0}, {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1343,6 +1344,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zkt", &gcc_options::x_riscv_zk_subext, MASK_ZKT}, {"zihintntl", &gcc_options::x_riscv_zi_subext, MASK_ZIHINTNTL}, + {"zihintpause", &gcc_options::x_riscv_zi_subext, MASK_ZIHINTPAUSE}, {"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ}, {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM}, diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index 79681d759628..554fb7f69bb0 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -122,7 +122,8 @@ AVAIL (clmul_zbkc32_or_zbc32, (TARGET_ZBKC || TARGET_ZBC) && !TARGET_64BIT) AVAIL (clmul_zbkc64_or_zbc64, (TARGET_ZBKC || TARGET_ZBC) && TARGET_64BIT) AVAIL (clmulr_zbc32, TARGET_ZBC && !TARGET_64BIT) AVAIL (clmulr_zbc64, TARGET_ZBC && TARGET_64BIT) -AVAIL (always, (!0)) +AVAIL (hint_pause, TARGET_ZIHINTPAUSE) +AVAIL (hint_pause_pseudo, !TARGET_ZIHINTPAUSE) /* Construct a riscv_builtin_description from the given arguments. @@ -179,7 +180,8 @@ static const struct riscv_builtin_description riscv_builtins[] = { DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float), DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float), - DIRECT_NO_TARGET_BUILTIN (pause, RISCV_VOID_FTYPE, always), + RISCV_BUILTIN (pause, "pause", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE, hint_pause), + RISCV_BUILTIN (pause_insn, "pause", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE, hint_pause_pseudo), }; /* Index I is the function declaration for riscv_builtins[I], or null if the diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 28d9b81bd800..a6c3e0c9098f 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -102,10 +102,12 @@ enum riscv_entity #define MASK_ZICSR (1 << 0) #define MASK_ZIFENCEI (1 << 1) #define MASK_ZIHINTNTL (1 << 2) +#define MASK_ZIHINTPAUSE (1 << 3) #define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0) #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0) #define TARGET_ZIHINTNTL ((riscv_zi_subext & MASK_ZIHINTNTL) != 0) +#define TARGET_ZIHINTPAUSE ((riscv_zi_subext & MASK_ZIHINTPAUSE) != 0) #define MASK_ZAWRS (1 << 0) #define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 688fd697255b..a6cdb32e9408 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2192,9 +2192,14 @@ (define_insn "riscv_pause" [(unspec_volatile [(const_int 0)] UNSPECV_PAUSE)] - "" + "TARGET_ZIHINTPAUSE" "pause") +(define_insn "riscv_pause_insn" + [(unspec_volatile [(const_int 0)] UNSPECV_PAUSE)] + "" + ".insn\t0x0100000f") + ;; ;; .................... ;; diff --git a/gcc/testsuite/gcc.target/riscv/builtin_pause.c b/gcc/testsuite/gcc.target/riscv/builtin_pause.c deleted file mode 100644 index 9250937cabb9..000000000000 --- a/gcc/testsuite/gcc.target/riscv/builtin_pause.c +++ /dev/null @@ -1,10 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2" } */ - -void test_pause() -{ - __builtin_riscv_pause (); -} - -/* { dg-final { scan-assembler "pause" } } */ - diff --git a/gcc/testsuite/gcc.target/riscv/zihintpause-1.c b/gcc/testsuite/gcc.target/riscv/zihintpause-1.c new file mode 100644 index 000000000000..fc86efe55902 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zihintpause-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_zihintpause -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +void +test () +{ + __builtin_riscv_pause (); +} + +/* { dg-final { scan-assembler-times "\tpause" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zihintpause-2.c b/gcc/testsuite/gcc.target/riscv/zihintpause-2.c new file mode 100644 index 000000000000..4eaca95e9f02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zihintpause-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32i_zihintpause -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +void +test () +{ + __builtin_riscv_pause (); +} + +/* { dg-final { scan-assembler-times "\tpause" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zihintpause-noarch.c b/gcc/testsuite/gcc.target/riscv/zihintpause-noarch.c new file mode 100644 index 000000000000..7ce5cba90d51 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zihintpause-noarch.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i -mabi=lp64" { target { rv64 } } } */ +/* { dg-options "-march=rv32i -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +void +test () +{ + __builtin_riscv_pause (); +} + +/* { dg-final { scan-assembler-times "0x0100000f" 1 } } */ From patchwork Thu Aug 10 02:25:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 1819666 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=IRWd4WEF; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RLrPt4P7mz1yYl for ; Thu, 10 Aug 2023 12:25:54 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 961B13857341 for ; Thu, 10 Aug 2023 02:25:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 961B13857341 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691634352; bh=gHrdmNJCoAiZHX2OcysJrxZHdUBSb+/Zac2GVNUYWaY=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=IRWd4WEFA/kv89NHrmTskZe7dENxMfXzm6qfHx7ScRBZN2ppj6CXCi+1pngFsb9cf TkXYh1qvoiBfMcDoDPuHiz/wezqRN6Og+X99u+pt/+cOppuR+2Cr3FUUkuxytfuEw7 1zUzkv9RGmfCrK5g0mCMxt8uzjbG8sIpooqiBkkY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 2FE0A3858288 for ; Thu, 10 Aug 2023 02:25:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2FE0A3858288 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 61C10300089; Thu, 10 Aug 2023 02:25:32 +0000 (UTC) To: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Andrew Waterman , Jim Wilson , Jeff Law Cc: gcc-patches@gcc.gnu.org Subject: [RFC PATCH v2 2/2] RISC-V: Fix documentation of __builtin_riscv_pause Date: Thu, 10 Aug 2023 02:25:07 +0000 Message-ID: <0d5372a64666bc70e72a781d81798e141a6ca208.1691634305.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Gcc-patches From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Tsukasa OI This built-in does not imply the 'Xgnuzihintpausestate' extension. It does not change architectural state (because all HINTs are prohibited from doing that). gcc/ChangeLog: * doc/extend.texi: Fix the description of __builtin_riscv_pause. --- gcc/doc/extend.texi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 89c5b4ea2b20..7ebbe70c78d6 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -21570,9 +21570,9 @@ Returns the value that is currently set in the @samp{tp} register. @enddefbuiltin @defbuiltin{void __builtin_riscv_pause (void)} -Generates the @code{pause} (hint) machine instruction. This implies the -Xgnuzihintpausestate extension, which redefines the @code{pause} instruction to -change architectural state. +Generates the @code{pause} (hint) machine instruction. If the target implements +the Zihintpause extension, it indicates that the current hart should be +temporarily paused or slowed down. @enddefbuiltin @node RISC-V Vector Intrinsics