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[98.210.197.24]) by smtp.gmail.com with ESMTPSA id jw22-20020a170903279600b001b9da42cd7dsm5801092plb.279.2023.07.22.14.48.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Jul 2023 14:48:09 -0700 (PDT) From: Vineet Gupta To: gcc-patches@gcc.gnu.org, Manolis Tsamis Cc: kito.cheng@gmail.com, Jeff Law , Palmer Dabbelt , gnu-toolchain@rivosinc.com, Philipp Tomsich , Vineet Gupta Subject: [Committed] RISC-V: optim const DF +0.0 store to mem [PR/110748] Date: Sat, 22 Jul 2023 14:48:05 -0700 Message-Id: <20230722214805.297932-1-vineetg@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <032e1546-8d92-e274-37b8-9d8d5438b679@rivosinc.com> References: <032e1546-8d92-e274-37b8-9d8d5438b679@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Fixes: ef85d150b5963 ("RISC-V: Enable TARGET_SUPPORTS_WIDE_INT") DF +0.0 is bitwise all zeros so int x0 store to mem can be used to optimize it. void zd(double *) { *d = 0.0; } currently: | fmv.d.x fa5,zero | fsd fa5,0(a0) | ret With patch | sd zero,0(a0) | ret The fix updates predicate const_0_operand() so reg_or_0_operand () now includes const_double, enabling movdf expander -> riscv_legitimize_move () to generate below vs. an intermediate set (reg:DF) const_double:DF | (insn 6 3 0 2 (set (mem:DF (reg/v/f:DI 134 [ d ]) | (const_double:DF 0.0 [0x0.0p+0])) This change also enables such insns to be recog() by later passes. The md pattern "*movdf_hardfloat_rv64" despite already supporting the needed constraints {"m","G"} mem/const 0.0 was failing to match because the additional condition check reg_or_0_operand() was failing due to missing const_double. This failure to recog() was triggering an ICE when testing the in-flight f-m-o patches and is how all of this started, but then was deemed to be an independent optimization of it's own [1]. [1] https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624857.html Its worthwhile to note all the set peices were already there and working up until my own commit mentioned at top regressed the whole thing. Ran thru full multilib testsuite and no surprises. There was 1 false failure due to random string "lw" appearing in lto build assembler output, which is also fixed here. gcc/ChangeLog: PR target/110748 * config/riscv/predicates.md (const_0_operand): Add back const_double. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr110748-1.c: New Test. * gcc.target/riscv/xtheadfmv-fmv.c: Add '\t' around test patterns to avoid random string matches. Signed-off-by: Vineet Gupta --- gcc/config/riscv/predicates.md | 2 +- gcc/testsuite/gcc.target/riscv/pr110748-1.c | 10 ++++++++++ gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c | 8 ++++---- 3 files changed, 15 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr110748-1.c diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 5a22c77f0cd0..9db28c2def7e 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -58,7 +58,7 @@ (match_test "INTVAL (op) + 1 != 0"))) (define_predicate "const_0_operand" - (and (match_code "const_int,const_wide_int,const_vector") + (and (match_code "const_int,const_wide_int,const_double,const_vector") (match_test "op == CONST0_RTX (GET_MODE (op))"))) (define_predicate "const_1_operand" diff --git a/gcc/testsuite/gcc.target/riscv/pr110748-1.c b/gcc/testsuite/gcc.target/riscv/pr110748-1.c new file mode 100644 index 000000000000..2f5bc08aae72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr110748-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target hard_float } */ +/* { dg-options "-march=rv64g -mabi=lp64d -O2" } */ + + +void zd(double *d) { *d = 0.0; } +void zf(float *f) { *f = 0.0; } + +/* { dg-final { scan-assembler-not "\tfmv\\.d\\.x\t" } } */ +/* { dg-final { scan-assembler-not "\tfmv\\.s\\.x\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c index 1036044291e7..89eb48bed1b9 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c @@ -18,7 +18,7 @@ d2ll (double d) /* { dg-final { scan-assembler "th.fmv.hw.x" } } */ /* { dg-final { scan-assembler "fmv.x.w" } } */ /* { dg-final { scan-assembler "th.fmv.x.hw" } } */ -/* { dg-final { scan-assembler-not "sw" } } */ -/* { dg-final { scan-assembler-not "fld" } } */ -/* { dg-final { scan-assembler-not "fsd" } } */ -/* { dg-final { scan-assembler-not "lw" } } */ +/* { dg-final { scan-assembler-not "\tsw\t" } } */ +/* { dg-final { scan-assembler-not "\tfld\t" } } */ +/* { dg-final { scan-assembler-not "\tfsd\t" } } */ +/* { dg-final { scan-assembler-not "\tlw\t" } } */