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Wed, 19 Jul 2023 03:06:27 +0000 Received: from smtpav04.fra02v.mail.ibm.com (smtpav04.fra02v.mail.ibm.com [10.20.54.103]) by smtprelay07.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 36J36OOQ30343646 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 19 Jul 2023 03:06:24 GMT Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 985F02004F; Wed, 19 Jul 2023 03:06:24 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1FA4220040; Wed, 19 Jul 2023 03:06:23 +0000 (GMT) Received: from [9.200.144.106] (unknown [9.200.144.106]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 19 Jul 2023 03:06:22 +0000 (GMT) Message-ID: <7b77c8d6-d052-6606-e8b8-b441cf2543b9@linux.ibm.com> Date: Wed, 19 Jul 2023 11:06:22 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Content-Language: en-US To: gcc-patches Cc: Segher Boessenkool , David , "Kewen.Lin" , Peter Bergner Subject: [PATCH-2, rs6000] Don't widen shift mode when target has rotate/mask instruction on original mode [PR93738] X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: j4cQHXYuK0xHXUYnAcQNmfpDjUvdxzYW X-Proofpoint-GUID: JAZt35dQDej_QSUm0LIqaRTtmuok0YuY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-18_19,2023-07-18_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 impostorscore=0 mlxscore=0 suspectscore=0 clxscore=1015 mlxlogscore=999 adultscore=0 malwarescore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307190027 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: HAO CHEN GUI via Gcc-patches From: HAO CHEN GUI Reply-To: HAO CHEN GUI Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, The patch relies on the fist patch. The reason of the change is also described in the first patch. This patch implements the target hook have_rotate_and_mask. It also modifies some test cases. The regression of rlwimi-2.c is fixed. For rlwinm-0.c and rlwinm-2.c, one more 32bit rotate/mask instruction is generated and one less 64bit rotate/mask instruction. The patch passed regression test on Power Linux platforms. Test shows the patch has no performance regression on SPECint. Thanks Gui Haochen ChangeLog rs6000: implement target hook have_rotate_and_mask gcc/ PR target/93738 * config/rs6000/rs6000.cc (TARGET_HAVE_ROTATE_AND_MASK): Define. (rs6000_have_rotate_and_mask): New function. gcc/testsuite/ PR target/93738 * gcc.target/powerpc/rlwimi-2.c: Adjust the number of 64bit and 32bit rotate instuctions. * gcc.target/powerpc/rlwinm-0.c: Likewise. * gcc.target/powerpc/rlwinm-2.c: Likewise. patch.diff diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 44b448d2ba6..98873afddb4 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1764,6 +1764,9 @@ static const struct attribute_spec rs6000_attribute_table[] = #undef TARGET_CONST_ANCHOR #define TARGET_CONST_ANCHOR 0x8000 +#undef TARGET_HAVE_ROTATE_AND_MASK +#define TARGET_HAVE_ROTATE_AND_MASK rs6000_have_rotate_and_mask + /* Processor table. */ @@ -29097,6 +29100,17 @@ rs6000_opaque_type_invalid_use_p (gimple *stmt) return false; } +bool +rs6000_have_rotate_and_mask (machine_mode mode) +{ + gcc_assert (SCALAR_INT_MODE_P (mode)); + + if (mode == SImode || mode == DImode) + return true; + + return false; +} + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-rs6000.h" diff --git a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c index bafa371db73..62344a95aa0 100644 --- a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c +++ b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c @@ -6,10 +6,9 @@ /* { dg-final { scan-assembler-times {(?n)^\s+blr} 6750 } } */ /* { dg-final { scan-assembler-times {(?n)^\s+mr} 643 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+mr} 11 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 7790 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 6728 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1666 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 } } */ /* { dg-final { scan-assembler-times {(?n)^\s+mulli} 5036 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c b/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c index 4f4fca2d8ef..b6b1b227c7e 100644 --- a/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c +++ b/gcc/testsuite/gcc.target/powerpc/rlwinm-0.c @@ -7,10 +7,10 @@ /* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 3081 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 3197 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 3093 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 3094 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+rotlwi} 154 } } */ /* { dg-final { scan-assembler-times {(?n)^\s+srwi} 13 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {(?n)^\s+srdi} 13 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+srdi} 12 { target lp64 } } } */ #define SL diff --git a/gcc/testsuite/gcc.target/powerpc/rlwinm-2.c b/gcc/testsuite/gcc.target/powerpc/rlwinm-2.c index bddcfe2b76f..0315ca91dd7 100644 --- a/gcc/testsuite/gcc.target/powerpc/rlwinm-2.c +++ b/gcc/testsuite/gcc.target/powerpc/rlwinm-2.c @@ -7,9 +7,9 @@ /* { dg-final { scan-assembler-times {(?n)^\s+rldic} 2726 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 833 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 720 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rlwinm} 721 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+srwi} 13 { target ilp32 } } } */ -/* { dg-final { scan-assembler-times {(?n)^\s+srdi} 13 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+srdi} 12 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+mulli} 2518 } } */