From patchwork Thu Jul 13 16:45:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 1807380 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=nextmovesoftware.com header.i=@nextmovesoftware.com header.a=rsa-sha256 header.s=default header.b=grrIKjtQ; dkim-atps=neutral Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R20pl11wwz20ZZ for ; Fri, 14 Jul 2023 02:45:35 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 471A53858415 for ; Thu, 13 Jul 2023 16:45:32 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id A97543858D32 for ; Thu, 13 Jul 2023 16:45:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A97543858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=/jl9lLUJU628tvNkHFewy5+eN5T8f2xs4ndvCgj6xa0=; b=grrIKjtQj8eg+ESuASa5FPEJng bjUDIT+SiOw/wP1Gy3l+u5eGvPhzObIyXk5+NuKTRCLoIWXSsOAuhSjBgOsyW6FpyQcXexahOYuTp rTR72tI2xqI18JwiiqR0VEA10CUz836mTb8dTi7TXVjgC3tixgnUY49DOXYBKXqjF7hXfR3WZHrZ+ vmuSDqbSXf6frGArpijiVJH23O5efsVByAydIebLDjBQWcu6VpMN5cTba0Q5fnDI0NI9rqz5s31JV kZhpFwxRkVyfmIa/igMCkIvO1mmEvod2P0W2M1gJXcMjKmeIMmAAG3lAndSKMji+c0kNq9g6CLGP5 kXl8jcRQ==; Received: from [185.62.158.67] (port=61191 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1qJzRM-00050a-1p; Thu, 13 Jul 2023 12:45:16 -0400 From: "Roger Sayle" To: Cc: "'Uros Bizjak'" Subject: [x86_64 PATCH] Improved insv of DImode/DFmode {high, low}parts into TImode. Date: Thu, 13 Jul 2023 17:45:13 +0100 Message-ID: <03e401d9b5a9$661e42e0$325ac8a0$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: Adm1qJpCH9XzWlKKTkS0URY2GSNh2w== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This is the next piece towards a fix for (the x86_64 ABI issues affecting) PR 88873. This patch generalizes the recent tweak to ix86_expand_move for setting the highpart of a TImode reg from a DImode source using *insvti_highpart_1, to handle both DImode and DFmode sources, and also use the recently added *insvti_lowpart_1 for setting the lowpart. Although this is another intermediate step (not yet a fix), towards enabling *insvti and *concat* patterns to be candidates for TImode STV (by using V2DI/V2DF instructions), it already improves things a little. For the test case from PR 88873 typedef struct { double x, y; } s_t; typedef double v2df __attribute__ ((vector_size (2 * sizeof(double)))); s_t foo (s_t a, s_t b, s_t c) { return (s_t) { fma(a.x, b.x, c.x), fma (a.y, b.y, c.y) }; } With -O2 -march=cascadelake, GCC currently generates: Before (29 instructions): vmovq %xmm2, -56(%rsp) movq -56(%rsp), %rdx vmovq %xmm4, -40(%rsp) movq $0, -48(%rsp) movq %rdx, -56(%rsp) movq -40(%rsp), %rdx vmovq %xmm0, -24(%rsp) movq %rdx, -40(%rsp) movq -24(%rsp), %rsi movq -56(%rsp), %rax movq $0, -32(%rsp) vmovq %xmm3, -48(%rsp) movq -48(%rsp), %rcx vmovq %xmm5, -32(%rsp) vmovq %rax, %xmm6 movq -40(%rsp), %rax movq $0, -16(%rsp) movq %rsi, -24(%rsp) movq -32(%rsp), %rsi vpinsrq $1, %rcx, %xmm6, %xmm6 vmovq %rax, %xmm7 vmovq %xmm1, -16(%rsp) vmovapd %xmm6, %xmm3 vpinsrq $1, %rsi, %xmm7, %xmm7 vfmadd132pd -24(%rsp), %xmm7, %xmm3 vmovapd %xmm3, -56(%rsp) vmovsd -48(%rsp), %xmm1 vmovsd -56(%rsp), %xmm0 ret After (20 instructions): vmovq %xmm2, -56(%rsp) movq -56(%rsp), %rax vmovq %xmm3, -48(%rsp) vmovq %xmm4, -40(%rsp) movq -48(%rsp), %rcx vmovq %xmm5, -32(%rsp) vmovq %rax, %xmm6 movq -40(%rsp), %rax movq -32(%rsp), %rsi vpinsrq $1, %rcx, %xmm6, %xmm6 vmovq %xmm0, -24(%rsp) vmovq %rax, %xmm7 vmovq %xmm1, -16(%rsp) vmovapd %xmm6, %xmm2 vpinsrq $1, %rsi, %xmm7, %xmm7 vfmadd132pd -24(%rsp), %xmm7, %xmm2 vmovapd %xmm2, -56(%rsp) vmovsd -48(%rsp), %xmm1 vmovsd -56(%rsp), %xmm0 ret This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32} with no new failures. No testcase yet, as the above code will hopefully change dramatically with the next pieces. Ok for mainline? 2023-07-13 Roger Sayle gcc/ChangeLog * config/i386/i386-expand.cc (ix86_expand_move): Generalize special case inserting of 64-bit values into a TImode register, to handle both DImode and DFmode using either *insvti_lowpart_1 or *isnvti_highpart_1. Thanks again, Roger diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 92ffa4b..fe87f8e 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -542,22 +542,39 @@ ix86_expand_move (machine_mode mode, rtx operands[]) } } - /* Use *insvti_highpart_1 to set highpart of TImode register. */ + /* Special case inserting 64-bit values into a TImode register. */ if (TARGET_64BIT - && mode == DImode + && (mode == DImode || mode == DFmode) && SUBREG_P (op0) - && SUBREG_BYTE (op0) == 8 && GET_MODE (SUBREG_REG (op0)) == TImode && REG_P (SUBREG_REG (op0)) && REG_P (op1)) { - wide_int mask = wi::mask (64, false, 128); - rtx tmp = immed_wide_int_const (mask, TImode); - op0 = SUBREG_REG (op0); - tmp = gen_rtx_AND (TImode, copy_rtx (op0), tmp); - op1 = gen_rtx_ZERO_EXTEND (TImode, op1); - op1 = gen_rtx_ASHIFT (TImode, op1, GEN_INT (64)); - op1 = gen_rtx_IOR (TImode, tmp, op1); + /* Use *insvti_lowpart_1 to set lowpart. */ + if (SUBREG_BYTE (op0) == 0) + { + wide_int mask = wi::mask (64, true, 128); + rtx tmp = immed_wide_int_const (mask, TImode); + op0 = SUBREG_REG (op0); + tmp = gen_rtx_AND (TImode, copy_rtx (op0), tmp); + if (mode == DFmode) + op1 = force_reg (DImode, gen_lowpart (DImode, op1)); + op1 = gen_rtx_ZERO_EXTEND (TImode, op1); + op1 = gen_rtx_IOR (TImode, tmp, op1); + } + /* Use *insvti_highpart_1 to set highpart. */ + else if (SUBREG_BYTE (op0) == 8) + { + wide_int mask = wi::mask (64, false, 128); + rtx tmp = immed_wide_int_const (mask, TImode); + op0 = SUBREG_REG (op0); + tmp = gen_rtx_AND (TImode, copy_rtx (op0), tmp); + if (mode == DFmode) + op1 = force_reg (DImode, gen_lowpart (DImode, op1)); + op1 = gen_rtx_ZERO_EXTEND (TImode, op1); + op1 = gen_rtx_ASHIFT (TImode, op1, GEN_INT (64)); + op1 = gen_rtx_IOR (TImode, tmp, op1); + } } emit_insn (gen_rtx_SET (op0, op1));