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Content preview: - Add macros for Machine Security Configuration (mseccfg) CSR - Add macros to access/manipulate bits in msecfg CSR Signed-off-by: Himanshu Chauhan --- include/sbi/riscv_encoding.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:431 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org - Add macros for Machine Security Configuration (mseccfg) CSR - Add macros to access/manipulate bits in msecfg CSR Signed-off-by: Himanshu Chauhan Reviewed-by: Anup Patel --- include/sbi/riscv_encoding.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index 4ebed97..50071ad 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -663,6 +663,18 @@ #define CSR_MHPMEVENT30H 0x73e #define CSR_MHPMEVENT31H 0x73f +/* Machine Security Configuration CSR (mseccfg) */ +#define CSR_MSECCFG_LOWER 0x747 +#define CSR_MSECCFG_UPPER 0x757 +#define CSR_MSECCFG (CSR_MSECCFG_LOWER) + +#define MSECCFG_MML_SHIFT (0) +#define MSECCFG_MML (_UL(1) << MSECCFG_MML_SHIFT) +#define MSECCFG_MMWP_SHIFT (1) +#define MSECCFG_MMWP (_UL(1) << MSECCFG_MMWP_SHIFT) +#define MSECCFG_RLB_SHIFT (2) +#define MSECCFG_RLB (_UL(1) << MSECCFG_RLB_SHIFT) + /* Counter Overflow CSR */ #define CSR_SCOUNTOVF 0xda0 From patchwork Tue Jun 20 14:32:08 2023 Content-Type: text/plain; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: - Add a function to disable a given PMP entry. - Add a function to check if a given entry is disabled. Signed-off-by: Himanshu Chauhan --- include/sbi/riscv_asm.h | 6 ++++++ lib/sbi/riscv_asm.c | 43 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:432 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org - Add a function to disable a given PMP entry. - Add a function to check if a given entry is disabled. Signed-off-by: Himanshu Chauhan Reviewed-by: Anup Patel --- include/sbi/riscv_asm.h | 6 ++++++ lib/sbi/riscv_asm.c | 43 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/include/sbi/riscv_asm.h b/include/sbi/riscv_asm.h index 1ff36de..2c34635 100644 --- a/include/sbi/riscv_asm.h +++ b/include/sbi/riscv_asm.h @@ -181,6 +181,12 @@ int misa_xlen(void); /* Get RISC-V ISA string representation */ void misa_string(int xlen, char *out, unsigned int out_sz); +/* Disable pmp entry at a given index */ +int pmp_disable(unsigned int n); + +/* Check if the matching field is set */ +int is_pmp_entry_mapped(unsigned long entry); + int pmp_set(unsigned int n, unsigned long prot, unsigned long addr, unsigned long log2len); diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c index cd56553..0690721 100644 --- a/lib/sbi/riscv_asm.c +++ b/lib/sbi/riscv_asm.c @@ -246,6 +246,49 @@ static unsigned long ctz(unsigned long x) return ret; } +int pmp_disable(unsigned int n) +{ + int pmpcfg_csr, pmpcfg_shift; + unsigned long cfgmask, pmpcfg; + + if (n >= PMP_COUNT) + return SBI_EINVAL; + +#if __riscv_xlen == 32 + pmpcfg_csr = CSR_PMPCFG0 + (n >> 2); + pmpcfg_shift = (n & 3) << 3; +#elif __riscv_xlen == 64 + pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1; + pmpcfg_shift = (n & 7) << 3; +#else +# error "Unexpected __riscv_xlen" +#endif + + /* Clear the address matching bits to disable the pmp entry */ + cfgmask = ~(0xffUL << pmpcfg_shift); + pmpcfg = (csr_read_num(pmpcfg_csr) & cfgmask); + pmpcfg &= (~PMP_A << pmpcfg_shift); + + csr_write_num(pmpcfg_csr, pmpcfg); + + return SBI_OK; +} + +int is_pmp_entry_mapped(unsigned long entry) +{ + unsigned long prot; + unsigned long addr; + unsigned long log2len; + + pmp_get(entry, &prot, &addr, &log2len); + + /* If address matching bits are non-zero, the entry is enable */ + if (prot & PMP_A) + return true; + + return false; +} + int pmp_set(unsigned int n, unsigned long prot, unsigned long addr, unsigned long log2len) { From patchwork Tue Jun 20 14:32:09 2023 Content-Type: text/plain; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Smepmp specification defines a truth table based on which the access is allowed to different modes. This patch adds different flags based on this truth table. Signed-off-by: Himanshu Chauhan --- include/sbi/sbi_domain.h | 51 +++++++++++++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 6 deletions(-) Content analysis details: (0.6 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:533 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.8 UPPERCASE_50_75 message body is 50-75% uppercase X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Smepmp specification defines a truth table based on which the access is allowed to different modes. This patch adds different flags based on this truth table. Signed-off-by: Himanshu Chauhan Reviewed-by: Anup Patel --- include/sbi/sbi_domain.h | 51 +++++++++++++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 6 deletions(-) diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h index b05bcf4..24d3dc1 100644 --- a/include/sbi/sbi_domain.h +++ b/include/sbi/sbi_domain.h @@ -43,6 +43,51 @@ struct sbi_domain_memregion { #define SBI_DOMAIN_MEMREGION_SU_WRITABLE (1UL << 4) #define SBI_DOMAIN_MEMREGION_SU_EXECUTABLE (1UL << 5) +#define SBI_DOMAIN_MEMREGION_ACCESS_MASK (0x3fUL) +#define SBI_DOMAIN_MEMREGION_M_ACCESS_MASK (0x7UL) +#define SBI_DOMAIN_MEMREGION_SU_ACCESS_MASK (0x38UL) + +#define SBI_DOMAIN_MEMREGION_SU_ACCESS_SHIFT (3) + +#define SBI_DOMAIN_MEMREGION_SHARED_RDONLY \ + (SBI_DOMAIN_MEMREGION_M_READABLE | \ + SBI_DOMAIN_MEMREGION_SU_READABLE) + +#define SBI_DOMAIN_MEMREGION_SHARED_SUX_MRX \ + (SBI_DOMAIN_MEMREGION_M_READABLE | \ + SBI_DOMAIN_MEMREGION_M_EXECUTABLE | \ + SBI_DOMAIN_MEMREGION_SU_EXECUTABLE) + +#define SBI_DOMAIN_MEMREGION_SHARED_SUX_MX \ + (SBI_DOMAIN_MEMREGION_M_EXECUTABLE | \ + SBI_DOMAIN_MEMREGION_SU_EXECUTABLE) + +#define SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW \ + (SBI_DOMAIN_MEMREGION_M_READABLE | \ + SBI_DOMAIN_MEMREGION_M_WRITABLE | \ + SBI_DOMAIN_MEMREGION_SU_READABLE| \ + SBI_DOMAIN_MEMREGION_SU_WRITABLE) + +#define SBI_DOMAIN_MEMREGION_SHARED_SUR_MRW \ + (SBI_DOMAIN_MEMREGION_M_READABLE | \ + SBI_DOMAIN_MEMREGION_M_WRITABLE | \ + SBI_DOMAIN_MEMREGION_SU_READABLE) + +#define SBI_DOMAIN_MEMREGION_IS_SHARED(_flags) \ + ((_flags == SBI_DOMAIN_MEMREGION_SHARED_RDONLY) || \ + (_flags == SBI_DOMAIN_MEMREGION_SHARED_SUX_MRX) || \ + (_flags == SBI_DOMAIN_MEMREGION_SHARED_SUX_MX) || \ + (_flags == SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW)|| \ + (_flags == SBI_DOMAIN_MEMREGION_SHARED_SUR_MRW)) + +#define SBI_DOMAIN_MEMREGION_M_ONLY_ACCESS(__flags) \ + ((__flags & SBI_DOMAIN_MEMREGION_M_ACCESS_MASK) && \ + !(__flags & SBI_DOMAIN_MEMREGION_SU_ACCESS_MASK)) + +#define SBI_DOMAIN_MEMREGION_SU_ONLY_ACCESS(__flags) \ + ((__flags & SBI_DOMAIN_MEMREGION_SU_ACCESS_MASK) && \ + !(__flags & SBI_DOMAIN_MEMREGION_M_ACCESS_MASK)) + /** Bit to control if permissions are enforced on all modes */ #define SBI_DOMAIN_MEMREGION_ENF_PERMISSIONS (1UL << 6) @@ -78,12 +123,6 @@ struct sbi_domain_memregion { (SBI_DOMAIN_MEMREGION_SU_EXECUTABLE | \ SBI_DOMAIN_MEMREGION_M_EXECUTABLE) -#define SBI_DOMAIN_MEMREGION_ACCESS_MASK (0x3fUL) -#define SBI_DOMAIN_MEMREGION_M_ACCESS_MASK (0x7UL) -#define SBI_DOMAIN_MEMREGION_SU_ACCESS_MASK (0x38UL) - -#define SBI_DOMAIN_MEMREGION_SU_ACCESS_SHIFT (3) - #define SBI_DOMAIN_MEMREGION_MMIO (1UL << 31) unsigned long flags; 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Tue, 20 Jun 2023 07:32:26 -0700 (PDT) Received: from saptrishi.dc1.ventanamicro.com ([2409:40f2:100b:244b:e36c:3899:a3b9:b8a2]) by smtp.gmail.com with ESMTPSA id p18-20020a62ab12000000b0063afb08afeesm1420002pff.67.2023.06.20.07.32.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 07:32:26 -0700 (PDT) From: Himanshu Chauhan To: opensbi@lists.infradead.org Cc: Himanshu Chauhan Subject: [PATCH 4/6] lib: sbi: Add detection of Smepmp from ISA string in FDT Date: Tue, 20 Jun 2023 20:02:10 +0530 Message-Id: <20230620143212.2701598-5-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230620143212.2701598-1-hchauhan@ventanamicro.com> References: <20230620143212.2701598-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230620_073228_825574_1A53ADCC X-CRM114-Status: GOOD ( 19.67 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: - To enable Smepmp, the ISA string in FDT should have "smepmp" string. This patch adds support for parsing of Smepmp in ISA string. - A bit is reserved for Smepmp in extensions member of sbi_hart_feat [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:433 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org - To enable Smepmp, the ISA string in FDT should have "smepmp" string. This patch adds support for parsing of Smepmp in ISA string. - A bit is reserved for Smepmp in extensions member of sbi_hart_features which is set if Smepmp is detected in FDT. - A utilty function is added to check if Smepmp is detected and enabled. - In sbi_boot_print_hart, a print is added to display the state of Smepmp. Signed-off-by: Himanshu Chauhan --- include/sbi/sbi_hart.h | 3 + include/sbi_utils/fdt/fdt_helper.h | 3 + lib/sbi/sbi_hart.c | 8 +++ lib/sbi/sbi_init.c | 2 + lib/utils/fdt/fdt_helper.c | 111 +++++++++++++++++++++++++++++ platform/generic/platform.c | 5 ++ 6 files changed, 132 insertions(+) diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h index 95b40e7..9582b52 100644 --- a/include/sbi/sbi_hart.h +++ b/include/sbi/sbi_hart.h @@ -36,6 +36,8 @@ enum sbi_hart_extensions { SBI_HART_EXT_SMSTATEEN, /** HART has Sstc extension */ SBI_HART_EXT_SSTC, + /** HART has Smepmp */ + SBI_HART_EXT_SMEPMP, /** Maximum index of Hart extension */ SBI_HART_EXT_MAX, @@ -66,6 +68,7 @@ static inline ulong sbi_hart_expected_trap_addr(void) unsigned int sbi_hart_mhpm_count(struct sbi_scratch *scratch); void sbi_hart_delegation_dump(struct sbi_scratch *scratch, const char *prefix, const char *suffix); +unsigned int sbi_hart_smepmp_supported(struct sbi_scratch *scratch); unsigned int sbi_hart_pmp_count(struct sbi_scratch *scratch); unsigned long sbi_hart_pmp_granularity(struct sbi_scratch *scratch); unsigned int sbi_hart_pmp_addrbits(struct sbi_scratch *scratch); diff --git a/include/sbi_utils/fdt/fdt_helper.h b/include/sbi_utils/fdt/fdt_helper.h index 39d7f3a..5c928ff 100644 --- a/include/sbi_utils/fdt/fdt_helper.h +++ b/include/sbi_utils/fdt/fdt_helper.h @@ -56,6 +56,9 @@ int fdt_parse_max_enabled_hart_id(void *fdt, u32 *max_hartid); int fdt_parse_timebase_frequency(void *fdt, unsigned long *freq); +int fdt_parse_isa_extensions(void *fdt, unsigned int hard_id, + unsigned long *extensions); + int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset, struct platform_uart_data *uart); diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c index 6e52cbd..c328243 100644 --- a/lib/sbi/sbi_hart.c +++ b/lib/sbi/sbi_hart.c @@ -260,6 +260,14 @@ unsigned int sbi_hart_pmp_count(struct sbi_scratch *scratch) return hfeatures->pmp_count; } +unsigned int sbi_hart_smepmp_supported(struct sbi_scratch *scratch) +{ + struct sbi_hart_features *hfeatures = + sbi_scratch_offset_ptr(scratch, hart_features_offset); + + return !!(hfeatures->extensions & (_UL(1) << SBI_HART_EXT_SMEPMP)); +} + unsigned long sbi_hart_pmp_granularity(struct sbi_scratch *scratch) { struct sbi_hart_features *hfeatures = diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c index 423e6d8..31d2c3e 100644 --- a/lib/sbi/sbi_init.c +++ b/lib/sbi/sbi_init.c @@ -173,6 +173,8 @@ static void sbi_boot_print_hart(struct sbi_scratch *scratch, u32 hartid) misa_string(xlen, str, sizeof(str)); sbi_printf("Boot HART Base ISA : %s\n", str); sbi_hart_get_extensions_str(scratch, str, sizeof(str)); + sbi_printf("SMEPMP : %sDetected\n", + (sbi_hart_smepmp_supported(scratch) ? "" : "Not ")); sbi_printf("Boot HART ISA Extensions : %s\n", str); sbi_printf("Boot HART PMP Count : %d\n", sbi_hart_pmp_count(scratch)); diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c index a88a4ba..db9d4c3 100644 --- a/lib/utils/fdt/fdt_helper.c +++ b/lib/utils/fdt/fdt_helper.c @@ -12,6 +12,7 @@ #include #include #include +#include /* for hart extension enums */ #include #include #include @@ -313,6 +314,116 @@ int fdt_parse_timebase_frequency(void *fdt, unsigned long *freq) return 0; } +static int fdt_get_isa_string(void *fdt, unsigned int hartid, + const char **isa_string) +{ + int err, cpu_offset, cpus_offset, len; + u32 c_hartid; + const fdt32_t *val; + + if (!fdt) + return SBI_EINVAL; + + cpus_offset = fdt_path_offset(fdt, "/cpus"); + if (cpus_offset < 0) + return cpus_offset; + + fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) { + err = fdt_parse_hart_id(fdt, cpu_offset, &c_hartid); + if (err) + continue; + + if (!fdt_node_is_enabled(fdt, cpu_offset)) + continue; + + if (c_hartid == hartid) { + val = fdt_getprop(fdt, cpu_offset, "riscv,isa", &len); + if (val && len > 0) { + *isa_string = (const char *)val; + return 0; + } + } + } + + return SBI_EINVAL; +} + +#define RISCV_ISA_EXT_NAME_LEN_MAX 32 + +int fdt_parse_isa_extensions(void *fdt, unsigned int hartid, + unsigned long *extensions) +{ + size_t i, j, isa_len; + char mstr[RISCV_ISA_EXT_NAME_LEN_MAX]; + const char *isa = NULL; + + if (fdt_get_isa_string(fdt, hartid, &isa)) + return SBI_EINVAL; + + if (!isa) + return SBI_EINVAL; + + i = 0; + isa_len = strlen(isa); + + if (isa[i] == 'r' || isa[i] == 'R') + i++; + else + return SBI_EINVAL; + + if (isa[i] == 'v' || isa[i] == 'V') + i++; + else + return SBI_EINVAL; + + if (isa[i] == '3' || isa[i+1] == '2') + i += 2; + else if (isa[i] == '6' || isa[i+1] == '4') + i += 2; + else + return SBI_EINVAL; + + /* Skip base ISA extentions */ + for (; i < isa_len; i++) { + if (isa[i] == '_') + break; + } + + while (i < isa_len) { + if (isa[i] != '_') { + i++; + continue; + } + + /* Skip the '_' character */ + i++; + + /* Extract the multi-letter extension name */ + j = 0; + while ((i < isa_len) && (isa[i] != '_') && + (j < (sizeof(mstr) - 1))) + mstr[j++] = isa[i++]; + mstr[j] = '\0'; + + /* Skip empty multi-letter extension name */ + if (!j) + continue; + +#define SET_ISA_EXT_MAP(name, bit) \ + do { \ + if (!strcmp(mstr, name)) { \ + __set_bit(bit, extensions); \ + continue; \ + } \ + } while (false) \ + + SET_ISA_EXT_MAP("smepmp", SBI_HART_EXT_SMEPMP); +#undef SET_ISA_EXT_MAP + } + + return 0; +} + static int fdt_parse_uart_node_common(void *fdt, int nodeoffset, struct platform_uart_data *uart, unsigned long default_freq, diff --git a/platform/generic/platform.c b/platform/generic/platform.c index 0c9cd95..24c0fa9 100644 --- a/platform/generic/platform.c +++ b/platform/generic/platform.c @@ -215,6 +215,11 @@ static int generic_extensions_init(struct sbi_hart_features *hfeatures) return generic_plat->extensions_init(generic_plat_match, hfeatures); + /* Parse the ISA string from FDT and enable the listed extensions */ + if (fdt_parse_isa_extensions(fdt_get_address(), current_hartid(), + &hfeatures->extensions)) + return 0; + return 0; } From patchwork Tue Jun 20 14:38:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Himanshu Chauhan X-Patchwork-Id: 1797364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=hZ1XS457; dkim=fail reason="signature verification failed" (2048-bit key; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: - If Smepmp is enabled, the access flags of an entry are determined based on truth table defined in Smepmp. - First PMP entry (index 0) is reserved. - Existing boot PMP entries start from index 1. - S [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:d29 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org - If Smepmp is enabled, the access flags of an entry are determined based on truth table defined in Smepmp. - First PMP entry (index 0) is reserved. - Existing boot PMP entries start from index 1. - Since enabling Smepmp revokes the access privileges of the M-mode software on S/U-mode region, first PMP entry is used to map/unmap the shared memory between M and S/U-mode. This allows a temporary access window for the M-mode software to read/write to S/U-mode memory region. Signed-off-by: Himanshu Chauhan --- include/sbi/sbi_hart.h | 17 ++++ lib/sbi/sbi_domain.c | 14 +++- lib/sbi/sbi_hart.c | 176 ++++++++++++++++++++++++++++++++++++----- lib/sbi/sbi_init.c | 22 +++--- 4 files changed, 197 insertions(+), 32 deletions(-) diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h index 9582b52..9fb9f53 100644 --- a/include/sbi/sbi_hart.h +++ b/include/sbi/sbi_hart.h @@ -43,6 +43,21 @@ enum sbi_hart_extensions { SBI_HART_EXT_MAX, }; +/* + * Smepmp enforces access boundaries between M-mode and + * S/U-mode. When it is enabled, the PMPs are programmed + * such that M-mode doesn't have access to S/U-mode memory. + * + * To give M-mode R/W access to the shared memory between M and + * S/U-mode, first entry is reserved. It is disabled at boot. + * When shared memory access is required, the physical address + * should be programmed into the first PMP entry with R/W + * permissions to the M-mode. Once the work is done, it should be + * unmapped. sbi_hart_map_saddr/sbi_hart_unmap_saddr function + * pair should be used to map/unmap the shared memory. + */ +#define SBI_SMEPMP_RESV_ENTRY 0 + struct sbi_hart_features { bool detected; int priv_version; @@ -74,6 +89,8 @@ unsigned long sbi_hart_pmp_granularity(struct sbi_scratch *scratch); unsigned int sbi_hart_pmp_addrbits(struct sbi_scratch *scratch); unsigned int sbi_hart_mhpm_bits(struct sbi_scratch *scratch); int sbi_hart_pmp_configure(struct sbi_scratch *scratch); +int sbi_hart_map_saddr(unsigned long base, unsigned long size); +int sbi_hart_unmap_saddr(void); int sbi_hart_priv_version(struct sbi_scratch *scratch); void sbi_hart_get_priv_version_str(struct sbi_scratch *scratch, char *version_str, int nvstr); diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c index 38a5902..acd0f74 100644 --- a/lib/sbi/sbi_domain.c +++ b/lib/sbi/sbi_domain.c @@ -772,11 +772,17 @@ int sbi_domain_init(struct sbi_scratch *scratch, u32 cold_hartid) root.fw_region_inited = true; - /* Root domain allow everything memory region */ + /* + * Allow SU RWX on rest of the memory region. Since pmp entries + * have implicit priority on index, previous entries will + * deny access to SU on M-mode region. Also, M-mode will not + * have access to SU region while previous entries will allow + * access to M-mode regions. + */ sbi_domain_memregion_init(0, ~0UL, - (SBI_DOMAIN_MEMREGION_READABLE | - SBI_DOMAIN_MEMREGION_WRITEABLE | - SBI_DOMAIN_MEMREGION_EXECUTABLE), + (SBI_DOMAIN_MEMREGION_SU_READABLE | + SBI_DOMAIN_MEMREGION_SU_WRITABLE | + SBI_DOMAIN_MEMREGION_SU_EXECUTABLE), &root_memregs[root_memregs_count++]); /* Root domain memory region end */ diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c index c328243..9678e37 100644 --- a/lib/sbi/sbi_hart.c +++ b/lib/sbi/sbi_hart.c @@ -292,11 +292,122 @@ unsigned int sbi_hart_mhpm_bits(struct sbi_scratch *scratch) return hfeatures->mhpm_bits; } +/* + * Returns Smepmp flags for a given domain and region based on permissions. + */ +unsigned int sbi_hart_get_smepmp_flags(struct sbi_scratch *scratch, + struct sbi_domain *dom, + struct sbi_domain_memregion *reg) +{ + unsigned int pmp_flags = 0; + + if (SBI_DOMAIN_MEMREGION_IS_SHARED(reg->flags)) { + /* Read only for both M and SU modes */ + if ((reg->flags & SBI_DOMAIN_MEMREGION_ACCESS_MASK) + == SBI_DOMAIN_MEMREGION_SHARED_RDONLY) + pmp_flags = (PMP_R | PMP_W | PMP_X); + + /* Execute for SU but Read/Execute for M mode */ + else if ((reg->flags & SBI_DOMAIN_MEMREGION_ACCESS_MASK) + == SBI_DOMAIN_MEMREGION_SHARED_SUX_MRX) + /* locked region */ + pmp_flags = (PMP_L | PMP_W | PMP_X); + + /* Execute only for both M and SU modes */ + else if ((reg->flags & SBI_DOMAIN_MEMREGION_ACCESS_MASK) + == SBI_DOMAIN_MEMREGION_SHARED_SUX_MX) + pmp_flags = (PMP_L | PMP_W); + + /* Read/Write for both M and SU modes */ + else if ((reg->flags & SBI_DOMAIN_MEMREGION_ACCESS_MASK) + == SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW) + pmp_flags = (PMP_W | PMP_X); + + /* Read only for SU mode but Read/Write for M mode */ + else if ((reg->flags & SBI_DOMAIN_MEMREGION_ACCESS_MASK) + == SBI_DOMAIN_MEMREGION_SHARED_SUR_MRW) + pmp_flags = (PMP_W); + } else if (SBI_DOMAIN_MEMREGION_M_ONLY_ACCESS(reg->flags)) { + /* + * When smepmp is supported and used, M region cannot have RWX + * permissions on any region. + */ + if ((reg->flags & SBI_DOMAIN_MEMREGION_M_ACCESS_MASK) + == SBI_DOMAIN_MEMREGION_M_RWX) { + sbi_printf("%s: M-mode only regions cannot have" + "RWX permissions\n", __func__); + return 0; + } + + /* M-mode only access regions are always locked */ + pmp_flags |= PMP_L; + + if (reg->flags & SBI_DOMAIN_MEMREGION_M_READABLE) + pmp_flags |= PMP_R; + if (reg->flags & SBI_DOMAIN_MEMREGION_M_WRITABLE) + pmp_flags |= PMP_W; + if (reg->flags & SBI_DOMAIN_MEMREGION_M_EXECUTABLE) + pmp_flags |= PMP_X; + } else if (SBI_DOMAIN_MEMREGION_SU_ONLY_ACCESS(reg->flags)) { + if (reg->flags & SBI_DOMAIN_MEMREGION_SU_READABLE) + pmp_flags |= PMP_R; + if (reg->flags & SBI_DOMAIN_MEMREGION_SU_WRITABLE) + pmp_flags |= PMP_W; + if (reg->flags & SBI_DOMAIN_MEMREGION_SU_EXECUTABLE) + pmp_flags |= PMP_X; + } + + return pmp_flags; +} + +int sbi_hart_map_saddr(unsigned long addr, unsigned long size) +{ + /* shared R/W access for M and S/U mode */ + unsigned int pmp_flags = (PMP_W | PMP_X); + unsigned long order, base = 0; + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); + + /* If Smepmp is not supported no special mapping is required */ + if (!sbi_hart_smepmp_supported(scratch)) + return SBI_OK; + + if (is_pmp_entry_mapped(SBI_SMEPMP_RESV_ENTRY)) + return SBI_ENOSPC; + + for (order = log2roundup(size) ; order <= __riscv_xlen; order++) { + if (order < __riscv_xlen) { + base = addr & ~((1UL << order) - 1UL); + if ((base <= addr) && + (addr < (base + (1UL << order))) && + (base <= (addr + size - 1UL)) && + ((addr + size - 1UL) < (base + (1UL << order)))) + break; + } else { + return SBI_EFAIL; + } + } + + pmp_set(SBI_SMEPMP_RESV_ENTRY, pmp_flags, base, order); + + return SBI_OK; +} + +int sbi_hart_unmap_saddr(void) +{ + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); + + if (!sbi_hart_smepmp_supported(scratch)) + return SBI_OK; + + return pmp_disable(SBI_SMEPMP_RESV_ENTRY); +} + int sbi_hart_pmp_configure(struct sbi_scratch *scratch) { struct sbi_domain_memregion *reg; struct sbi_domain *dom = sbi_domain_thishart_ptr(); - unsigned int pmp_idx = 0, pmp_flags, pmp_bits, pmp_gran_log2; + unsigned int pmp_idx = 0; + unsigned int pmp_flags, pmp_bits, pmp_gran_log2; unsigned int pmp_count = sbi_hart_pmp_count(scratch); unsigned long pmp_addr = 0, pmp_addr_max = 0; @@ -307,36 +418,63 @@ int sbi_hart_pmp_configure(struct sbi_scratch *scratch) pmp_bits = sbi_hart_pmp_addrbits(scratch) - 1; pmp_addr_max = (1UL << pmp_bits) | ((1UL << pmp_bits) - 1); + if (sbi_hart_smepmp_supported(scratch)) { + /* Reserve first entry for dynamic shared mappings */ + pmp_idx = SBI_SMEPMP_RESV_ENTRY + 1; + + /* + * Set the RLB now so that, we can write to entries + * even if some entries are locked. + */ + csr_write(CSR_MSECCFG, MSECCFG_RLB); + + /* Disable the reserved entry */ + pmp_disable(SBI_SMEPMP_RESV_ENTRY); + } + sbi_domain_for_each_memregion(dom, reg) { if (pmp_count <= pmp_idx) break; pmp_flags = 0; - /* - * If permissions are to be enforced for all modes on this - * region, the lock bit should be set. - */ - if (reg->flags & SBI_DOMAIN_MEMREGION_ENF_PERMISSIONS) - pmp_flags |= PMP_L; - - if (reg->flags & SBI_DOMAIN_MEMREGION_SU_READABLE) - pmp_flags |= PMP_R; - if (reg->flags & SBI_DOMAIN_MEMREGION_SU_WRITABLE) - pmp_flags |= PMP_W; - if (reg->flags & SBI_DOMAIN_MEMREGION_SU_EXECUTABLE) - pmp_flags |= PMP_X; + if (sbi_hart_smepmp_supported(scratch)) { + pmp_flags = sbi_hart_get_smepmp_flags(scratch, dom, reg); + + if (pmp_flags == 0) + return 0; + } else { + /* + * If permissions are to be enforced for all modes on + * this region, the lock bit should be set. + */ + if (reg->flags & SBI_DOMAIN_MEMREGION_ENF_PERMISSIONS) + pmp_flags |= PMP_L; + + if (reg->flags & SBI_DOMAIN_MEMREGION_SU_READABLE) + pmp_flags |= PMP_R; + if (reg->flags & SBI_DOMAIN_MEMREGION_SU_WRITABLE) + pmp_flags |= PMP_W; + if (reg->flags & SBI_DOMAIN_MEMREGION_SU_EXECUTABLE) + pmp_flags |= PMP_X; + } pmp_addr = reg->base >> PMP_SHIFT; - if (pmp_gran_log2 <= reg->order && pmp_addr < pmp_addr_max) + if (pmp_gran_log2 <= reg->order && pmp_addr < pmp_addr_max) { pmp_set(pmp_idx++, pmp_flags, reg->base, reg->order); - else { - sbi_printf("Can not configure pmp for domain %s", dom->name); - sbi_printf(" because memory region address %lx or size %lx is not in range\n", - reg->base, reg->order); + } else { + sbi_printf("Can not configure pmp for domain %s because" + " memory region address 0x%lx or size 0x%lx " + "is not in range.\n", dom->name, reg->base, + reg->order); } } + if (sbi_hart_smepmp_supported(scratch)) { + /* All entries are programmed. Enable MML bit. */ + csr_write(CSR_MSECCFG, (MSECCFG_RLB | MSECCFG_MML)); + } + /* * As per section 3.7.2 of privileged specification v1.12, * virtual address translations can be speculatively performed diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c index 31d2c3e..82078d9 100644 --- a/lib/sbi/sbi_init.c +++ b/lib/sbi/sbi_init.c @@ -358,13 +358,6 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid) sbi_hart_hang(); } - rc = sbi_hart_pmp_configure(scratch); - if (rc) { - sbi_printf("%s: PMP configure failed (error %d)\n", - __func__, rc); - sbi_hart_hang(); - } - /* * Note: Platform final initialization should be after finalizing * domains so that it sees correct domain assignment and PMP @@ -394,6 +387,17 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid) sbi_boot_print_hart(scratch, hartid); + /* + * Configure PMP at last because if SMEPMP is detected, + * M-mode access to the S/U space will be rescinded. + */ + rc = sbi_hart_pmp_configure(scratch); + if (rc) { + sbi_printf("%s: PMP configure failed (error %d)\n", + __func__, rc); + sbi_hart_hang(); + } + wake_coldboot_harts(scratch, hartid); count = sbi_scratch_offset_ptr(scratch, init_count_offset); @@ -447,11 +451,11 @@ static void __noreturn init_warm_startup(struct sbi_scratch *scratch, if (rc) sbi_hart_hang(); - rc = sbi_hart_pmp_configure(scratch); + rc = sbi_platform_final_init(plat, false); if (rc) sbi_hart_hang(); - rc = sbi_platform_final_init(plat, false); + rc = sbi_hart_pmp_configure(scratch); if (rc) sbi_hart_hang(); From patchwork Tue Jun 20 14:38:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Himanshu Chauhan X-Patchwork-Id: 1797365 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; 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Signed-off-by: Himanshu Chauhan --- lib/sbi/sbi_ecall_dbcn.c | 3 +++ 1 file changed, 3 insertions(+) Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:631 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org With Smepmp enabled, it is necessary for shared memory from S/U mode to be mapped/unmapped before and after read/write of the memory region. Signed-off-by: Himanshu Chauhan Reviewed-by: Anup Patel --- lib/sbi/sbi_ecall_dbcn.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/sbi/sbi_ecall_dbcn.c b/lib/sbi/sbi_ecall_dbcn.c index e0b892c..3724d70 100644 --- a/lib/sbi/sbi_ecall_dbcn.c +++ b/lib/sbi/sbi_ecall_dbcn.c @@ -14,6 +14,7 @@ #include #include #include +#include static int sbi_ecall_dbcn_handler(unsigned long extid, unsigned long funcid, const struct sbi_trap_regs *regs, @@ -43,10 +44,12 @@ static int sbi_ecall_dbcn_handler(unsigned long extid, unsigned long funcid, regs->a1, regs->a0, smode, SBI_DOMAIN_READ|SBI_DOMAIN_WRITE)) return SBI_ERR_INVALID_PARAM; + sbi_hart_map_saddr(regs->a1, regs->a0); if (funcid == SBI_EXT_DBCN_CONSOLE_WRITE) *out_val = sbi_nputs((const char *)regs->a1, regs->a0); else *out_val = sbi_ngets((char *)regs->a1, regs->a0); + sbi_hart_unmap_saddr(); return 0; case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: sbi_putc(regs->a0);