From patchwork Thu Apr 20 12:11:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 1771331 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Q2Gnq3TKDz1ybF for ; Thu, 20 Apr 2023 22:15:26 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A7A413858434 for ; Thu, 20 Apr 2023 12:15:23 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from esa4.mentor.iphmx.com (esa4.mentor.iphmx.com [68.232.137.252]) by sourceware.org (Postfix) with ESMTPS id 63C3D3858D37 for ; Thu, 20 Apr 2023 12:15:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 63C3D3858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com X-IronPort-AV: E=Sophos;i="5.99,212,1677571200"; d="scan'208";a="3042143" Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa4.mentor.iphmx.com with ESMTP; 20 Apr 2023 04:11:42 -0800 IronPort-SDR: 0hLYmk93QPfV04kNfbMkDilI+TL8L7QrXMQz9iaBQwKp2baBekhbFC+twd6wJMK6bNu2tl/XFT k9k+77mwDknJD15TURUfJ7JoWLHIB0atyTcZhwQL279NKh4DnlZ1qiBJtRiBKB+7Le8QC3ohrI WF636wXR2hFu/Qv2zP/aQ510/KUKtfMxWCRBz/Ekk7SRI8GarRkA1cCFtO9eh1t6BlijxUdBGG ngQdlkDL9wLpV2FdZkYpt1+ggZhwiy+uUlEubUhkJgOLY+x5KMpP1iVUiTzulE18Q+eU0zFpGZ t10= Message-ID: Date: Thu, 20 Apr 2023 13:11:36 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Content-Language: en-GB To: "gcc-patches@gcc.gnu.org" From: Andrew Stubbs Subject: [committed] amdgcn: bug fix ldexp insn X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: svr-ies-mbx-14.mgc.mentorg.com (139.181.222.14) To svr-ies-mbx-11.mgc.mentorg.com (139.181.222.11) X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The hardfp division patch exposed a flaw in the ldexp pattern at -O0; the compiler was trying to use out-of-range immediates on VOP3 instruction encodings. This patch changes the constraints appropriately, and also takes the opportunity to combine the two patterns into one using the newly available SV_FP iterator. Andrew amdgcn: bug fix ldexp insn The vop3 instructions don't support B constraint immediates. Also, take the use the SV_FP iterator to delete a redundant pattern. gcc/ChangeLog: * config/gcn/gcn-valu.md (vnsi, VnSI): Add scalar modes. (ldexp3): Delete. (ldexp3): Change "B" to "A". diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 4a40a9d8d4c..44c48468dd6 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -208,7 +208,9 @@ (define_mode_attr SCALAR_MODE (V64HF "HF") (V64SF "SF") (V64DI "DI") (V64DF "DF")]) (define_mode_attr vnsi - [(V2QI "v2si") (V2HI "v2si") (V2HF "v2si") (V2SI "v2si") + [(QI "si") (HI "si") (SI "si") + (HF "si") (SF "si") (DI "si") (DF "si") + (V2QI "v2si") (V2HI "v2si") (V2HF "v2si") (V2SI "v2si") (V2SF "v2si") (V2DI "v2si") (V2DF "v2si") (V4QI "v4si") (V4HI "v4si") (V4HF "v4si") (V4SI "v4si") (V4SF "v4si") (V4DI "v4si") (V4DF "v4si") @@ -222,7 +224,9 @@ (define_mode_attr vnsi (V64SF "v64si") (V64DI "v64si") (V64DF "v64si")]) (define_mode_attr VnSI - [(V2QI "V2SI") (V2HI "V2SI") (V2HF "V2SI") (V2SI "V2SI") + [(QI "SI") (HI "SI") (SI "SI") + (HF "SI") (SF "SI") (DI "SI") (DF "SI") + (V2QI "V2SI") (V2HI "V2SI") (V2HF "V2SI") (V2SI "V2SI") (V2SF "V2SI") (V2DI "V2SI") (V2DF "V2SI") (V4QI "V4SI") (V4HI "V4SI") (V4HF "V4SI") (V4SI "V4SI") (V4SF "V4SI") (V4DI "V4SI") (V4DF "V4SI") @@ -3043,21 +3047,10 @@ (define_expand "2" ; Implement ldexp pattern -(define_insn "ldexp3" - [(set (match_operand:FP 0 "register_operand" "=v") - (unspec:FP - [(match_operand:FP 1 "gcn_alu_operand" "vB") - (match_operand:SI 2 "gcn_alu_operand" "vSvA")] - UNSPEC_LDEXP))] - "" - "v_ldexp%i0\t%0, %1, %2" - [(set_attr "type" "vop3a") - (set_attr "length" "8")]) - (define_insn "ldexp3" - [(set (match_operand:V_FP 0 "register_operand" "= v") - (unspec:V_FP - [(match_operand:V_FP 1 "gcn_alu_operand" " vB") + [(set (match_operand:SV_FP 0 "register_operand" "= v") + (unspec:SV_FP + [(match_operand:SV_FP 1 "gcn_alu_operand" " vA") (match_operand: 2 "gcn_alu_operand" "vSvA")] UNSPEC_LDEXP))] ""