From patchwork Tue Mar 28 10:10:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1762247 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4Pm5743wJsz1yYs for ; Tue, 28 Mar 2023 21:11:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232949AbjC1KLL (ORCPT ); Tue, 28 Mar 2023 06:11:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232989AbjC1KK7 (ORCPT ); Tue, 28 Mar 2023 06:10:59 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 048BC35B6; Tue, 28 Mar 2023 03:10:34 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.98,297,1673881200"; d="scan'208";a="154048960" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 28 Mar 2023 19:10:24 +0900 Received: from localhost.localdomain (unknown [10.226.92.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 857CB40071F7; Tue, 28 Mar 2023 19:10:21 +0900 (JST) From: Biju Das To: Linus Walleij , Philipp Zabel Cc: Biju Das , Geert Uytterhoeven , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Chris Paterson , Prabhakar Mahadev Lad Subject: [PATCH v7 02/10] drivers: pinctrl: renesas: Add RZ/G2L POEG driver support Date: Tue, 28 Mar 2023 11:10:03 +0100 Message-Id: <20230328101011.185594-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> References: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org The output pins of the RZ/G2L general PWM timer (GPT) can be disabled by using the port output enabling function for the GPT (POEG). Add basic user control support to enable/disable output from GPT by using poeg char device. Signed-off-by: Biju Das --- v6->v7: * Used DT to handle the system configuration * Added poeg char device for user control support to enable/disable output from GPT * Replaced iowrite32/ioread32-> writel/readl * Dropped of_match_ptr from .of_match_table v5->v6: * Dropped sysfs and is handled in generic driver. v4->v5: * Updated kernel version in sysfs doc. v3->v4: * Updated commit description. v2->v3: * Added sysfs documentation for output_disable * PWM_RZG2L_GPT implies ARCH_RZG2L. So removed ARCH_RZG2L dependency * Used dev_get_drvdata to get device data * Replaced sprintf->sysfs_emit in show(). v1->v2: * Renamed the file poeg-rzg2l->rzg2l-poeg * Removed the macro POEGG as there is only single register and updated rzg2l_poeg_write() and rzg2l_poeg_read() * Updated error handling in probe() Ref->v1: * Moved driver files from soc to pincontrol directory * Updated KConfig --- drivers/pinctrl/renesas/Kconfig | 2 + drivers/pinctrl/renesas/Makefile | 2 + drivers/pinctrl/renesas/poeg/Kconfig | 11 + drivers/pinctrl/renesas/poeg/Makefile | 2 + drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 299 ++++++++++++++++++++++ include/linux/pinctrl/rzg2l-poeg.h | 15 ++ 6 files changed, 331 insertions(+) create mode 100644 drivers/pinctrl/renesas/poeg/Kconfig create mode 100644 drivers/pinctrl/renesas/poeg/Makefile create mode 100644 drivers/pinctrl/renesas/poeg/rzg2l-poeg.c create mode 100644 include/linux/pinctrl/rzg2l-poeg.h diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 77730dc548ed..42e030ae2783 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -303,4 +303,6 @@ config PINCTRL_PFC_SHX3 bool "pin control support for SH-X3" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO +source "drivers/pinctrl/renesas/poeg/Kconfig" + endmenu diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 3e776955bd4b..03338920725e 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -51,6 +51,8 @@ obj-$(CONFIG_PINCTRL_RZG2L) += pinctrl-rzg2l.o obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o obj-$(CONFIG_PINCTRL_RZV2M) += pinctrl-rzv2m.o +obj-$(CONFIG_POEG_RZG2L) += poeg/ + ifeq ($(CONFIG_COMPILE_TEST),y) CFLAGS_pfc-sh7203.o += -I$(srctree)/arch/sh/include/cpu-sh2a CFLAGS_pfc-sh7264.o += -I$(srctree)/arch/sh/include/cpu-sh2a diff --git a/drivers/pinctrl/renesas/poeg/Kconfig b/drivers/pinctrl/renesas/poeg/Kconfig new file mode 100644 index 000000000000..306e8ae81cb2 --- /dev/null +++ b/drivers/pinctrl/renesas/poeg/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 +config POEG_RZG2L + tristate "Renesas RZ/G2L poeg support" + depends on PWM_RZG2L_GPT || COMPILE_TEST + depends on HAS_IOMEM + help + This driver exposes the Port Output Enable for GPT(POEG) found + in Renesas RZ/G2L alike SoCs. + + To compile this driver as a module, choose M here: the module + will be called rzg2l-poeg. diff --git a/drivers/pinctrl/renesas/poeg/Makefile b/drivers/pinctrl/renesas/poeg/Makefile new file mode 100644 index 000000000000..610bdd6182be --- /dev/null +++ b/drivers/pinctrl/renesas/poeg/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_POEG_RZG2L) += rzg2l-poeg.o diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c new file mode 100644 index 000000000000..30e75954af76 --- /dev/null +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G2L Port Output Enable for GPT (POEG) driver + * + * Copyright (C) 2023 Renesas Electronics Corporation + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define POEGG_SSF BIT(3) + +#define RZG2L_POEG_MAX_INDEX 3 + +#define RZG2L_GPT_MAX_HW_CHANNELS 8 +#define RZG2L_GPT_INVALID_CHANNEL 0xff + +enum poeg_conf { + POEG_USER_CTRL = BIT(0), + POEG_GPT_BOTH_HIGH = BIT(1), + POEG_GPT_BOTH_LOW = BIT(2), + POEG_GPT_DEAD_TIME = BIT(3), + POEG_EXT_PIN_CTRL = BIT(4), + POEG_GPT_BOTH_HIGH_LOW = BIT(1) | BIT(2), + POEG_GPT_BOTH_HIGH_DEAD_TIME = BIT(1) | BIT(3), + POEG_GPT_BOTH_LOW_DEAD_TIME = BIT(2) | BIT(3), + POEG_GPT_ALL = BIT(1) | BIT(2) | BIT(3) +}; + +static struct class *poeg_class; +static dev_t g_poeg_dev; +static int minor_n; + +struct rzg2l_poeg_chip { + struct device *gpt_dev; + struct reset_control *rstc; + void __iomem *mmio; + struct cdev poeg_cdev; + u8 gpt_channels[RZG2L_GPT_MAX_HW_CHANNELS]; + u8 index; + u32 cfg; + int minor_n; +}; + +static void rzg2l_poeg_write(struct rzg2l_poeg_chip *chip, u32 data) +{ + writel(data, chip->mmio); +} + +static u32 rzg2l_poeg_read(struct rzg2l_poeg_chip *chip) +{ + return readl(chip->mmio); +} + +static int rzg2l_poeg_output_disable_user(struct rzg2l_poeg_chip *chip, + bool enable) +{ + u32 reg_val; + + reg_val = rzg2l_poeg_read(chip); + if (enable) + reg_val |= POEGG_SSF; + else + reg_val &= ~POEGG_SSF; + + rzg2l_poeg_write(chip, reg_val); + + return 0; +} + +static ssize_t rzg2l_poeg_chrdev_write(struct file *filp, + const char __user *buf, + size_t len, loff_t *f_ps) +{ + struct rzg2l_poeg_chip *const chip = filp->private_data; + struct poeg_cmd cmd; + + if (copy_from_user(&cmd, buf, sizeof(cmd))) + return -EFAULT; + + switch (cmd.val) { + case RZG2L_POEG_USR_CTRL_ENABLE_CMD: + rzg2l_poeg_output_disable_user(chip, true); + break; + case RZG2L_POEG_USR_CTRL_DISABLE_CMD: + rzg2l_poeg_output_disable_user(chip, false); + break; + default: + return -EINVAL; + } + + return len; +} + +static int rzg2l_poeg_chrdev_open(struct inode *inode, struct file *filp) +{ + struct rzg2l_poeg_chip *const chip = container_of(inode->i_cdev, + typeof(*chip), + poeg_cdev); + + filp->private_data = chip; + + return nonseekable_open(inode, filp); +} + +static int rzg2l_poeg_chrdev_release(struct inode *inode, struct file *filp) +{ + filp->private_data = NULL; + + return 0; +} + +static const struct file_operations poeg_fops = { + .owner = THIS_MODULE, + .write = rzg2l_poeg_chrdev_write, + .open = rzg2l_poeg_chrdev_open, + .release = rzg2l_poeg_chrdev_release, +}; + +static const struct of_device_id rzg2l_poeg_of_table[] = { + { .compatible = "renesas,rzg2l-poeg", }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzg2l_poeg_of_table); + +static void rzg2l_poeg_cleanup(void *data) +{ + struct rzg2l_poeg_chip *chip = data; + + put_device(chip->gpt_dev); +} + +static int rzg2l_poeg_probe(struct platform_device *pdev) +{ + struct platform_device *gpt_pdev = NULL; + struct rzg2l_poeg_chip *chip; + struct device_node *np; + struct device *cdev; + u32 cfg, val; + int ret; + + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + if (!of_property_read_u32(pdev->dev.of_node, "renesas,poeg-id", &val)) + chip->index = val; + + if (chip->index > RZG2L_POEG_MAX_INDEX) + return -EINVAL; + + np = of_parse_phandle(pdev->dev.of_node, "renesas,gpt", 0); + if (np) + gpt_pdev = of_find_device_by_node(np); + + of_node_put(np); + if (!gpt_pdev) + return -ENODEV; + + chip->gpt_dev = &gpt_pdev->dev; + ret = devm_add_action_or_reset(&pdev->dev, rzg2l_poeg_cleanup, chip); + if (ret < 0) + return ret; + + chip->mmio = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(chip->mmio)) + return PTR_ERR(chip->mmio); + + chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(chip->rstc)) + return dev_err_probe(&pdev->dev, PTR_ERR(chip->rstc), + "get reset failed\n"); + + ret = reset_control_deassert(chip->rstc); + if (ret) + return ret; + + platform_set_drvdata(pdev, chip); + pm_runtime_enable(&pdev->dev); + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "pm_runtime_resume_get failed: %d\n", ret); + goto err_pm_disable; + } + + if (!of_property_read_u32(pdev->dev.of_node, "renesas,poeg-config", &cfg)) { + switch (cfg) { + case POEG_USER_CTRL: + rzg2l_poeg_write(chip, POEGG_SSF); + break; + default: + ret = -EINVAL; + goto err_pm; + } + + chip->cfg = cfg; + + cdev_init(&chip->poeg_cdev, &poeg_fops); + chip->poeg_cdev.owner = THIS_MODULE; + ret = cdev_add(&chip->poeg_cdev, MKDEV(MAJOR(g_poeg_dev), minor_n), 1); + if (ret) + goto err_pm; + + cdev = device_create(poeg_class, NULL, + MKDEV(MAJOR(g_poeg_dev), minor_n), NULL, + "poeg%d", minor_n); + if (IS_ERR(cdev)) { + ret = PTR_ERR(cdev); + dev_err(&pdev->dev, + "Error %d creating device for port %u\n", + ret, minor_n); + goto free_cdev; + } + chip->minor_n = minor_n; + } + + minor_n++; + + return ret; + +free_cdev: + cdev_del(&chip->poeg_cdev); +err_pm: + pm_runtime_put(&pdev->dev); +err_pm_disable: + pm_runtime_disable(&pdev->dev); + reset_control_assert(chip->rstc); + return ret; +} + +static int rzg2l_poeg_remove(struct platform_device *pdev) +{ + struct rzg2l_poeg_chip *chip = platform_get_drvdata(pdev); + + device_destroy(poeg_class, MKDEV(MAJOR(g_poeg_dev), chip->minor_n)); + cdev_del(&chip->poeg_cdev); + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); + reset_control_assert(chip->rstc); + + return 0; +} + +static struct platform_driver rzg2l_poeg_driver = { + .driver = { + .name = "rzg2l-poeg", + .of_match_table = rzg2l_poeg_of_table + }, + .probe = rzg2l_poeg_probe, + .remove = rzg2l_poeg_remove +}; + +static int rzg2l_poeg_device_init(void) +{ + int err; + + err = alloc_chrdev_region(&g_poeg_dev, 0, 1, "poeg"); + if (err) + goto out; + + poeg_class = class_create("poeg"); + if (IS_ERR(poeg_class)) { + err = PTR_ERR(poeg_class); + goto err_free_chrdev; + } + + err = platform_driver_register(&rzg2l_poeg_driver); + if (err) + goto err_class_destroy; + + return 0; + +err_class_destroy: + class_destroy(poeg_class); +err_free_chrdev: + unregister_chrdev_region(g_poeg_dev, 1); +out: + return err; +} + +static void rzg2l_poeg_device_exit(void) +{ + platform_driver_unregister(&rzg2l_poeg_driver); + class_destroy(poeg_class); + unregister_chrdev_region(g_poeg_dev, 1); +} + +module_init(rzg2l_poeg_device_init); +module_exit(rzg2l_poeg_device_exit); + +MODULE_AUTHOR("Biju Das "); +MODULE_DESCRIPTION("Renesas RZ/G2L POEG Driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/pinctrl/rzg2l-poeg.h b/include/linux/pinctrl/rzg2l-poeg.h new file mode 100644 index 000000000000..32e7d07fc00e --- /dev/null +++ b/include/linux/pinctrl/rzg2l-poeg.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_POEG_RZG2L_H__ +#define __LINUX_POEG_RZG2L_H__ + +#include + +#define RZG2L_POEG_USR_CTRL_ENABLE_CMD 0 +#define RZG2L_POEG_USR_CTRL_DISABLE_CMD 1 + +struct poeg_cmd { + __u32 val; + __u8 channel; +}; + +#endif /* __LINUX_POEG_RZG2L_H__ */ From patchwork Tue Mar 28 10:10:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1762250 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4Pm57738rKz1yYp for ; Tue, 28 Mar 2023 21:11:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233054AbjC1KLO (ORCPT ); Tue, 28 Mar 2023 06:11:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233022AbjC1KLB (ORCPT ); Tue, 28 Mar 2023 06:11:01 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 470217684; Tue, 28 Mar 2023 03:10:37 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.98,297,1673881200"; d="scan'208";a="157440644" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 28 Mar 2023 19:10:28 +0900 Received: from localhost.localdomain (unknown [10.226.92.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 63FE140065AF; Tue, 28 Mar 2023 19:10:25 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v7 03/10] pwm: rzg2l-gpt: Add support for output disable request from gpt Date: Tue, 28 Mar 2023 11:10:04 +0100 Message-Id: <20230328101011.185594-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> References: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org When dead time error occurs or the GTIOCA pin output value is the same as the GTIOCB pin output value, output protection is required. GPT detects this condition and generates output disable requests to POEG based on the settings in the output disable request permission bits, such as GTINTAD.GRPDTE, GTINTAD.GRPABH, GTINTAD.GRPABL. After the POEG receives output disable requests from each channel and calculates external input using an OR operation, the POEG generates output disable requests to GPT. This patch adds support for output disable request from gpt, when same time output level is high. Signed-off-by: Biju Das --- drivers/pwm/pwm-rzg2l-gpt.c | 111 ++++++++++++++++++++++++++++++++++ include/linux/pwm/rzg2l-gpt.h | 32 ++++++++++ 2 files changed, 143 insertions(+) create mode 100644 include/linux/pwm/rzg2l-gpt.h diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 9f3e2f7635a8..2f138e95f752 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -32,6 +33,7 @@ #define RZG2L_GTUDDTYC 0x30 #define RZG2L_GTIOR 0x34 #define RZG2L_GTINTAD 0x38 +#define RZG2L_GTST 0x3c #define RZG2L_GTBER 0x40 #define RZG2L_GTCNT 0x48 #define RZG2L_GTCCRA 0x4c @@ -72,6 +74,12 @@ (FIELD_PREP(RZG2L_GTIOR_GTIOB, RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE) | RZG2L_GTIOR_OBE) #define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24) +#define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH BIT(29) + +#define RZG2L_GTST_OABHF BIT(29) +#define RZG2L_GTST_OABLF BIT(30) + +#define RZG2L_GTST_POEG_IRQ_MASK GENMASK(30, 28) #define RZG2L_GTCCR(i) (0x4c + 4 * (i)) @@ -431,6 +439,109 @@ static DEFINE_RUNTIME_DEV_PM_OPS(rzg2l_gpt_pm_ops, rzg2l_gpt_pm_runtime_suspend, rzg2l_gpt_pm_runtime_resume, NULL); +u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp) +{ + u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS; + struct rzg2l_gpt_chip *rzg2l_gpt; + unsigned int i; + u32 val = 0; + u32 offs; + u32 reg; + + rzg2l_gpt = dev_get_drvdata(dev); + for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + val <<= 3; + if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link)) + continue; + + offs = RZG2L_GET_CH_OFFS(i); + reg = rzg2l_gpt_read(rzg2l_gpt, offs + RZG2L_GTST); + val |= FIELD_GET(RZG2L_GTST_POEG_IRQ_MASK, reg); + } + + return val; +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_irq_status); + +int rzg2l_gpt_poeg_disable_req_clr(void *dev, u8 grp) +{ + u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS; + struct rzg2l_gpt_chip *rzg2l_gpt; + unsigned int i; + u32 offs; + u32 reg; + + rzg2l_gpt = dev_get_drvdata(dev); + for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link)) + continue; + + offs = RZG2L_GET_CH_OFFS(i); + reg = rzg2l_gpt_read(rzg2l_gpt, offs + RZG2L_GTST); + + if (reg & (RZG2L_GTST_OABHF | RZG2L_GTST_OABLF)) + rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTIOR, + RZG2L_GTIOR_OBE, 0); + } + + return 0; +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_clr); + +int rzg2l_gpt_pin_reenable(void *dev, u8 grp) +{ + u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS; + struct rzg2l_gpt_chip *rzg2l_gpt; + unsigned int i; + u32 offs; + + rzg2l_gpt = dev_get_drvdata(dev); + for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link)) + continue; + + offs = RZG2L_GET_CH_OFFS(i); + rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTIOR, + RZG2L_GTIOR_OBE, RZG2L_GTIOR_OBE); + } + return 0; +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_pin_reenable); + +static int rzg2l_gpt_poeg_disable_req_endisable(void *dev, u8 grp, int op, bool on) +{ + u8 bitpos = grp * RZG2L_MAX_HW_CHANNELS; + struct rzg2l_gpt_chip *rzg2l_gpt; + unsigned int i; + u32 offs; + + rzg2l_gpt = dev_get_drvdata(dev); + pm_runtime_get_sync(dev); + + for (i = 0; i < RZG2L_MAX_HW_CHANNELS; i++) { + if (!test_bit(bitpos + i, rzg2l_gpt->poeg_gpt_link)) + continue; + + offs = RZG2L_GET_CH_OFFS(i); + if (on) + rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTINTAD, op, op); + else + rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTINTAD, op, 0); + } + + pm_runtime_put(dev); + + return 0; +} + +int rzg2l_gpt_poeg_disable_req_both_high(void *dev, u8 grp, bool on) +{ + int id = RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH; + + return rzg2l_gpt_poeg_disable_req_endisable(dev, grp, id, on); +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_high); + static void rzg2l_gpt_reset_assert_pm_disable(void *data) { struct rzg2l_gpt_chip *rzg2l_gpt = data; diff --git a/include/linux/pwm/rzg2l-gpt.h b/include/linux/pwm/rzg2l-gpt.h new file mode 100644 index 000000000000..0fc13ab57420 --- /dev/null +++ b/include/linux/pwm/rzg2l-gpt.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_PWM_RZG2L_GPT_H__ +#define __LINUX_PWM_RZG2L_GPT_H__ + +#if IS_ENABLED(CONFIG_PWM_RZG2L_GPT) +u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp); +int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp); +int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp); +int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on); +#else +static inline u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp) +{ + return -ENODEV; +} + +static inline int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp) +{ + return -ENODEV; +} + +static inline int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp) +{ + return -ENODEV; +} + +static inline int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on) +{ + return -ENODEV; +} +#endif + +#endif /* __LINUX_PWM_RZG2L_GPT_H__ */ From patchwork Tue Mar 28 10:10:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1762252 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4Pm5790ls3z1yYr for ; Tue, 28 Mar 2023 21:11:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230269AbjC1KLP (ORCPT ); Tue, 28 Mar 2023 06:11:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233056AbjC1KLC (ORCPT ); Tue, 28 Mar 2023 06:11:02 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BFAAB6A68; Tue, 28 Mar 2023 03:10:38 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.98,297,1673881200"; d="scan'208";a="157440661" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 28 Mar 2023 19:10:31 +0900 Received: from localhost.localdomain (unknown [10.226.92.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id F13B240071EC; Tue, 28 Mar 2023 19:10:28 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v7 04/10] pinctrl: renesas: rzg2l-poeg: Add support for GPT Output-Disable Request Date: Tue, 28 Mar 2023 11:10:05 +0100 Message-Id: <20230328101011.185594-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> References: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch supports output-disable requests from GPT. When both outputs are high, gpt detects the condition and triggers an interrupt to POEG. POEG handles the interrupt and send notification to userspace. userspace handles the fault and issue a write call to cancel the disable output request. Signed-off-by: Biju Das --- drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 165 +++++++++++++++++++++- include/linux/pinctrl/rzg2l-poeg.h | 9 ++ 2 files changed, 173 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c index 30e75954af76..2683930309ca 100644 --- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -5,16 +5,23 @@ * Copyright (C) 2023 Renesas Electronics Corporation */ #include +#include #include +#include #include #include #include #include #include #include +#include +#include #include +#include +#define POEGG_IOCE BIT(5) #define POEGG_SSF BIT(3) +#define POEGG_IOCF BIT(1) #define RZG2L_POEG_MAX_INDEX 3 @@ -41,7 +48,10 @@ struct rzg2l_poeg_chip { struct device *gpt_dev; struct reset_control *rstc; void __iomem *mmio; + DECLARE_BITMAP(gpt_irq, 3); struct cdev poeg_cdev; + wait_queue_head_t events_wait; + DECLARE_KFIFO_PTR(events, struct poeg_event); u8 gpt_channels[RZG2L_GPT_MAX_HW_CHANNELS]; u8 index; u32 cfg; @@ -74,6 +84,76 @@ static int rzg2l_poeg_output_disable_user(struct rzg2l_poeg_chip *chip, return 0; } +static void rzg2l_poeg_config_irq(struct rzg2l_poeg_chip *chip) +{ + if (test_bit(RZG2L_GPT_OABHF, chip->gpt_irq)) + rzg2l_gpt_poeg_disable_req_both_high(chip->gpt_dev, chip->index, true); +} + +static irqreturn_t rzg2l_poeg_irq(int irq, void *ptr) +{ + struct rzg2l_poeg_chip *chip = ptr; + struct poeg_event ev; + u32 val; + + val = rzg2l_gpt_poeg_disable_req_irq_status(chip->gpt_dev, chip->index); + ev.channel = chip->index; + ev.gpt_disable_irq_status = val; + kfifo_in(&chip->events, &ev, 1); + wake_up_poll(&chip->events_wait, EPOLLIN); + + rzg2l_gpt_poeg_disable_req_clr(chip->gpt_dev, chip->index); + val = rzg2l_poeg_read(chip); + if (val & POEGG_IOCF) + val &= ~POEGG_IOCF; + + rzg2l_poeg_write(chip, val); + + return IRQ_HANDLED; +} + +static __poll_t rzg2l_poeg_chrdev_poll(struct file *filp, + struct poll_table_struct *pollt) +{ + struct rzg2l_poeg_chip *const chip = filp->private_data; + __poll_t events = 0; + + poll_wait(filp, &chip->events_wait, pollt); + if (!kfifo_is_empty(&chip->events)) + events = EPOLLIN | EPOLLRDNORM; + + return events; +} + +static ssize_t rzg2l_poeg_chrdev_read(struct file *filp, char __user *buf, + size_t len, loff_t *f_ps) +{ + struct rzg2l_poeg_chip *const chip = filp->private_data; + unsigned int copied; + int err; + + if (len < sizeof(struct poeg_event)) + return -EINVAL; + + do { + if (kfifo_is_empty(&chip->events)) { + if (filp->f_flags & O_NONBLOCK) + return -EAGAIN; + + err = wait_event_interruptible(chip->events_wait, + !kfifo_is_empty(&chip->events)); + if (err < 0) + return err; + } + + err = kfifo_to_user(&chip->events, buf, len, &copied); + if (err < 0) + return err; + } while (!copied); + + return copied; +} + static ssize_t rzg2l_poeg_chrdev_write(struct file *filp, const char __user *buf, size_t len, loff_t *f_ps) @@ -91,6 +171,12 @@ static ssize_t rzg2l_poeg_chrdev_write(struct file *filp, case RZG2L_POEG_USR_CTRL_DISABLE_CMD: rzg2l_poeg_output_disable_user(chip, false); break; + case RZG2L_POEG_GPT_CFG_IRQ_CMD: + rzg2l_poeg_config_irq(chip); + break; + case RZG2L_POEG_GPT_FAULT_CLR_CMD: + rzg2l_gpt_pin_reenable(chip->gpt_dev, chip->index); + break; default: return -EINVAL; } @@ -118,11 +204,63 @@ static int rzg2l_poeg_chrdev_release(struct inode *inode, struct file *filp) static const struct file_operations poeg_fops = { .owner = THIS_MODULE, + .read = rzg2l_poeg_chrdev_read, .write = rzg2l_poeg_chrdev_write, + .poll = rzg2l_poeg_chrdev_poll, .open = rzg2l_poeg_chrdev_open, .release = rzg2l_poeg_chrdev_release, }; +static bool rzg2l_poeg_get_linked_gpt_channels(struct platform_device *pdev, + struct rzg2l_poeg_chip *chip, + struct device_node *gpt_np, + u8 poeg_id) +{ + struct of_phandle_args of_args; + bool ret = false; + unsigned int i; + u32 poeg_grp; + int cells; + int err; + + cells = of_property_count_u32_elems(gpt_np, "renesas,poegs"); + if (cells == -EINVAL) + return ret; + + for (i = 0 ; i < RZG2L_GPT_MAX_HW_CHANNELS; i++) + chip->gpt_channels[i] = RZG2L_GPT_INVALID_CHANNEL; + + cells >>= 1; + for (i = 0; i < cells; i++) { + err = of_parse_phandle_with_fixed_args(gpt_np, + "renesas,poegs", 1, i, + &of_args); + if (err) { + dev_err(&pdev->dev, + "Failed to parse 'renesas,poegs' property\n"); + break; + } + + if (of_args.args[0] >= RZG2L_GPT_MAX_HW_CHANNELS) { + dev_err(&pdev->dev, "Invalid channel %d >= %d\n", + of_args.args[0], RZG2L_GPT_MAX_HW_CHANNELS); + of_node_put(of_args.np); + break; + } + + if (!of_property_read_u32(of_args.np, "renesas,poeg-id", &poeg_grp)) { + if (poeg_grp == poeg_id) { + chip->gpt_channels[of_args.args[0]] = poeg_id; + ret = true; + } + } + + of_node_put(of_args.np); + } + + return ret; +} + static const struct of_device_id rzg2l_poeg_of_table[] = { { .compatible = "renesas,rzg2l-poeg", }, { /* Sentinel */ } @@ -140,10 +278,11 @@ static int rzg2l_poeg_probe(struct platform_device *pdev) { struct platform_device *gpt_pdev = NULL; struct rzg2l_poeg_chip *chip; + bool gpt_linked = false; struct device_node *np; struct device *cdev; u32 cfg, val; - int ret; + int ret, irq; chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); if (!chip) @@ -159,6 +298,8 @@ static int rzg2l_poeg_probe(struct platform_device *pdev) if (np) gpt_pdev = of_find_device_by_node(np); + gpt_linked = rzg2l_poeg_get_linked_gpt_channels(pdev, chip, np, + chip->index); of_node_put(np); if (!gpt_pdev) return -ENODEV; @@ -172,6 +313,17 @@ static int rzg2l_poeg_probe(struct platform_device *pdev) if (IS_ERR(chip->mmio)) return PTR_ERR(chip->mmio); + if (gpt_linked) { + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = devm_request_irq(&pdev->dev, irq, rzg2l_poeg_irq, 0, + dev_name(&pdev->dev), chip); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "cannot get irq\n"); + } + chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(chip->rstc)) return dev_err_probe(&pdev->dev, PTR_ERR(chip->rstc), @@ -194,13 +346,20 @@ static int rzg2l_poeg_probe(struct platform_device *pdev) case POEG_USER_CTRL: rzg2l_poeg_write(chip, POEGG_SSF); break; + case POEG_GPT_BOTH_HIGH: + assign_bit(RZG2L_GPT_OABHF, chip->gpt_irq, true); + break; default: ret = -EINVAL; goto err_pm; } + if (cfg & POEG_GPT_ALL) + rzg2l_poeg_write(chip, POEGG_IOCE); + chip->cfg = cfg; + init_waitqueue_head(&chip->events_wait); cdev_init(&chip->poeg_cdev, &poeg_fops); chip->poeg_cdev.owner = THIS_MODULE; ret = cdev_add(&chip->poeg_cdev, MKDEV(MAJOR(g_poeg_dev), minor_n), 1); @@ -218,6 +377,9 @@ static int rzg2l_poeg_probe(struct platform_device *pdev) goto free_cdev; } chip->minor_n = minor_n; + ret = kfifo_alloc(&chip->events, 64, GFP_KERNEL); + if (ret) + goto free_cdev; } minor_n++; @@ -238,6 +400,7 @@ static int rzg2l_poeg_remove(struct platform_device *pdev) { struct rzg2l_poeg_chip *chip = platform_get_drvdata(pdev); + kfifo_free(&chip->events); device_destroy(poeg_class, MKDEV(MAJOR(g_poeg_dev), chip->minor_n)); cdev_del(&chip->poeg_cdev); pm_runtime_put(&pdev->dev); diff --git a/include/linux/pinctrl/rzg2l-poeg.h b/include/linux/pinctrl/rzg2l-poeg.h index 32e7d07fc00e..d21b70c219e6 100644 --- a/include/linux/pinctrl/rzg2l-poeg.h +++ b/include/linux/pinctrl/rzg2l-poeg.h @@ -4,8 +4,17 @@ #include +#define RZG2L_GPT_OABHF 1 + #define RZG2L_POEG_USR_CTRL_ENABLE_CMD 0 #define RZG2L_POEG_USR_CTRL_DISABLE_CMD 1 +#define RZG2L_POEG_GPT_CFG_IRQ_CMD 2 +#define RZG2L_POEG_GPT_FAULT_CLR_CMD 3 + +struct poeg_event { + __u32 gpt_disable_irq_status; + __u8 channel; +}; struct poeg_cmd { __u32 val; From patchwork Tue Mar 28 10:10:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1762253 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4Pm5795Hccz1yYs for ; Tue, 28 Mar 2023 21:11:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233035AbjC1KLQ (ORCPT ); Tue, 28 Mar 2023 06:11:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233060AbjC1KLD (ORCPT ); Tue, 28 Mar 2023 06:11:03 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E3EFD76B4; Tue, 28 Mar 2023 03:10:42 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.98,297,1673881200"; d="scan'208";a="157440675" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 28 Mar 2023 19:10:35 +0900 Received: from localhost.localdomain (unknown [10.226.92.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 8DC6A40078D3; Tue, 28 Mar 2023 19:10:32 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v7 05/10] pwm: rzg2l-gpt: Add support for output disable when both output low Date: Tue, 28 Mar 2023 11:10:06 +0100 Message-Id: <20230328101011.185594-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> References: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds support for output disable request from gpt, when same time output level is low. Signed-off-by: Biju Das --- drivers/pwm/pwm-rzg2l-gpt.c | 9 +++++++++ include/linux/pwm/rzg2l-gpt.h | 6 ++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 2f138e95f752..2291cc3cff39 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -75,6 +75,7 @@ #define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24) #define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH BIT(29) +#define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_LOW BIT(30) #define RZG2L_GTST_OABHF BIT(29) #define RZG2L_GTST_OABLF BIT(30) @@ -542,6 +543,14 @@ int rzg2l_gpt_poeg_disable_req_both_high(void *dev, u8 grp, bool on) } EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_high); +int rzg2l_gpt_poeg_disable_req_both_low(void *dev, u8 grp, bool on) +{ + int id = RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_LOW; + + return rzg2l_gpt_poeg_disable_req_endisable(dev, grp, id, on); +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_low); + static void rzg2l_gpt_reset_assert_pm_disable(void *data) { struct rzg2l_gpt_chip *rzg2l_gpt = data; diff --git a/include/linux/pwm/rzg2l-gpt.h b/include/linux/pwm/rzg2l-gpt.h index 0fc13ab57420..592bc2900c9e 100644 --- a/include/linux/pwm/rzg2l-gpt.h +++ b/include/linux/pwm/rzg2l-gpt.h @@ -7,6 +7,7 @@ u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp); int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp); int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp); int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on); +int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, bool on); #else static inline u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp) { @@ -27,6 +28,11 @@ static inline int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, { return -ENODEV; } + +static inline int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, bool on) +{ + return -ENODEV; +} #endif #endif /* __LINUX_PWM_RZG2L_GPT_H__ */ From patchwork Tue Mar 28 10:10:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1762255 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4Pm57J3RKjz1yYS for ; Tue, 28 Mar 2023 21:11:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230287AbjC1KLX (ORCPT ); Tue, 28 Mar 2023 06:11:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233022AbjC1KLO (ORCPT ); Tue, 28 Mar 2023 06:11:14 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 05C24618A; Tue, 28 Mar 2023 03:10:54 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.98,297,1673881200"; d="scan'208";a="154049005" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 28 Mar 2023 19:10:39 +0900 Received: from localhost.localdomain (unknown [10.226.92.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 5C91440071EC; Tue, 28 Mar 2023 19:10:36 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v7 06/10] pinctrl: renesas: rzg2l-poeg: output-disable request from GPT when both outputs are low. Date: Tue, 28 Mar 2023 11:10:07 +0100 Message-Id: <20230328101011.185594-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> References: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds support for output-disable requests from GPT, when both outputs are low. Signed-off-by: Biju Das --- drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 11 +++++++++++ include/linux/pinctrl/rzg2l-poeg.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c index 2683930309ca..b66d717d6bf4 100644 --- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -88,6 +88,10 @@ static void rzg2l_poeg_config_irq(struct rzg2l_poeg_chip *chip) { if (test_bit(RZG2L_GPT_OABHF, chip->gpt_irq)) rzg2l_gpt_poeg_disable_req_both_high(chip->gpt_dev, chip->index, true); + + if (test_bit(RZG2L_GPT_OABLF, chip->gpt_irq)) + rzg2l_gpt_poeg_disable_req_both_low(chip->gpt_dev, chip->index, true); + } static irqreturn_t rzg2l_poeg_irq(int irq, void *ptr) @@ -349,6 +353,13 @@ static int rzg2l_poeg_probe(struct platform_device *pdev) case POEG_GPT_BOTH_HIGH: assign_bit(RZG2L_GPT_OABHF, chip->gpt_irq, true); break; + case POEG_GPT_BOTH_LOW: + assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true); + break; + case POEG_GPT_BOTH_HIGH_LOW: + assign_bit(RZG2L_GPT_OABHF, chip->gpt_irq, true); + assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true); + break; default: ret = -EINVAL; goto err_pm; diff --git a/include/linux/pinctrl/rzg2l-poeg.h b/include/linux/pinctrl/rzg2l-poeg.h index d21b70c219e6..e1e0ba5b47a1 100644 --- a/include/linux/pinctrl/rzg2l-poeg.h +++ b/include/linux/pinctrl/rzg2l-poeg.h @@ -5,6 +5,7 @@ #include #define RZG2L_GPT_OABHF 1 +#define RZG2L_GPT_OABLF 2 #define RZG2L_POEG_USR_CTRL_ENABLE_CMD 0 #define RZG2L_POEG_USR_CTRL_DISABLE_CMD 1 From patchwork Tue Mar 28 10:10:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1762263 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4Pm57Q4NY6z1yYp for ; Tue, 28 Mar 2023 21:11:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232548AbjC1KL3 (ORCPT ); Tue, 28 Mar 2023 06:11:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232988AbjC1KLY (ORCPT ); Tue, 28 Mar 2023 06:11:24 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id EEFA07EEA; Tue, 28 Mar 2023 03:11:01 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.98,297,1673881200"; d="scan'208";a="157440694" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 28 Mar 2023 19:10:43 +0900 Received: from localhost.localdomain (unknown [10.226.92.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 32D9440078D3; Tue, 28 Mar 2023 19:10:39 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v7 07/10] pwm: rzg2l-gpt: Add support for output disable on dead time error Date: Tue, 28 Mar 2023 11:10:08 +0100 Message-Id: <20230328101011.185594-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> References: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds support for output disable request from gpt, when dead time error occurred. Signed-off-by: Biju Das --- drivers/pwm/pwm-rzg2l-gpt.c | 9 +++++++++ include/linux/pwm/rzg2l-gpt.h | 6 ++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 2291cc3cff39..c88a5bf9e31d 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -74,6 +74,7 @@ (FIELD_PREP(RZG2L_GTIOR_GTIOB, RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE) | RZG2L_GTIOR_OBE) #define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24) +#define RZG2L_GTINTAD_OUTPUT_DISABLE_DEADTIME_ERROR BIT(28) #define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_HIGH BIT(29) #define RZG2L_GTINTAD_OUTPUT_DISABLE_SAME_LEVEL_LOW BIT(30) @@ -551,6 +552,14 @@ int rzg2l_gpt_poeg_disable_req_both_low(void *dev, u8 grp, bool on) } EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_both_low); +int rzg2l_gpt_poeg_disable_req_deadtime_error(void *dev, u8 grp, bool on) +{ + int id = RZG2L_GTINTAD_OUTPUT_DISABLE_DEADTIME_ERROR; + + return rzg2l_gpt_poeg_disable_req_endisable(dev, grp, id, on); +} +EXPORT_SYMBOL_GPL(rzg2l_gpt_poeg_disable_req_deadtime_error); + static void rzg2l_gpt_reset_assert_pm_disable(void *data) { struct rzg2l_gpt_chip *rzg2l_gpt = data; diff --git a/include/linux/pwm/rzg2l-gpt.h b/include/linux/pwm/rzg2l-gpt.h index 592bc2900c9e..8a004c690c2a 100644 --- a/include/linux/pwm/rzg2l-gpt.h +++ b/include/linux/pwm/rzg2l-gpt.h @@ -8,6 +8,7 @@ int rzg2l_gpt_poeg_disable_req_clr(void *gpt_device, u8 grp); int rzg2l_gpt_pin_reenable(void *gpt_device, u8 grp); int rzg2l_gpt_poeg_disable_req_both_high(void *gpt_device, u8 grp, bool on); int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, bool on); +int rzg2l_gpt_poeg_disable_req_deadtime_error(void *gpt_device, u8 grp, bool on); #else static inline u32 rzg2l_gpt_poeg_disable_req_irq_status(void *dev, u8 grp) { @@ -33,6 +34,11 @@ static inline int rzg2l_gpt_poeg_disable_req_both_low(void *gpt_device, u8 grp, { return -ENODEV; } + +static inline int rzg2l_gpt_poeg_disable_req_deadtime_err(void *gpt_device, u8 grp, bool on) +{ + return -ENODEV; +} #endif #endif /* __LINUX_PWM_RZG2L_GPT_H__ */ From patchwork Tue Mar 28 10:10:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1762257 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4Pm57K2rhPz1yYS for ; Tue, 28 Mar 2023 21:11:25 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231932AbjC1KLY (ORCPT ); Tue, 28 Mar 2023 06:11:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233057AbjC1KLQ (ORCPT ); Tue, 28 Mar 2023 06:11:16 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2C84E7D84; Tue, 28 Mar 2023 03:10:56 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.98,297,1673881200"; d="scan'208";a="154049022" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 28 Mar 2023 19:10:46 +0900 Received: from localhost.localdomain (unknown [10.226.92.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id BBA7940071F7; Tue, 28 Mar 2023 19:10:43 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v7 08/10] pinctrl: renesas: rzg2l-poeg: output-disable request from GPT on dead time error Date: Tue, 28 Mar 2023 11:10:09 +0100 Message-Id: <20230328101011.185594-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> References: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds support for output-disable requests from GPT, when dead time error occurs. Signed-off-by: Biju Das --- drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 18 ++++++++++++++++++ include/linux/pinctrl/rzg2l-poeg.h | 1 + 2 files changed, 19 insertions(+) diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c index b66d717d6bf4..7576f756af3c 100644 --- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -92,6 +92,8 @@ static void rzg2l_poeg_config_irq(struct rzg2l_poeg_chip *chip) if (test_bit(RZG2L_GPT_OABLF, chip->gpt_irq)) rzg2l_gpt_poeg_disable_req_both_low(chip->gpt_dev, chip->index, true); + if (test_bit(RZG2L_GPT_DTEF, chip->gpt_irq)) + rzg2l_gpt_poeg_disable_req_deadtime_error(chip->gpt_dev, chip->index, true); } static irqreturn_t rzg2l_poeg_irq(int irq, void *ptr) @@ -356,10 +358,26 @@ static int rzg2l_poeg_probe(struct platform_device *pdev) case POEG_GPT_BOTH_LOW: assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true); break; + case POEG_GPT_DEAD_TIME: + assign_bit(RZG2L_GPT_DTEF, chip->gpt_irq, true); + break; case POEG_GPT_BOTH_HIGH_LOW: assign_bit(RZG2L_GPT_OABHF, chip->gpt_irq, true); assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true); break; + case POEG_GPT_BOTH_HIGH_DEAD_TIME: + assign_bit(RZG2L_GPT_OABHF, chip->gpt_irq, true); + assign_bit(RZG2L_GPT_DTEF, chip->gpt_irq, true); + break; + case POEG_GPT_BOTH_LOW_DEAD_TIME: + assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true); + assign_bit(RZG2L_GPT_DTEF, chip->gpt_irq, true); + break; + case POEG_GPT_ALL: + assign_bit(RZG2L_GPT_OABHF, chip->gpt_irq, true); + assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true); + assign_bit(RZG2L_GPT_DTEF, chip->gpt_irq, true); + break; default: ret = -EINVAL; goto err_pm; diff --git a/include/linux/pinctrl/rzg2l-poeg.h b/include/linux/pinctrl/rzg2l-poeg.h index e1e0ba5b47a1..5441de7f3751 100644 --- a/include/linux/pinctrl/rzg2l-poeg.h +++ b/include/linux/pinctrl/rzg2l-poeg.h @@ -4,6 +4,7 @@ #include +#define RZG2L_GPT_DTEF 0 #define RZG2L_GPT_OABHF 1 #define RZG2L_GPT_OABLF 2 From patchwork Tue Mar 28 10:10:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1762261 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4Pm57P3dGcz1yYS for ; Tue, 28 Mar 2023 21:11:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232893AbjC1KL2 (ORCPT ); Tue, 28 Mar 2023 06:11:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232709AbjC1KLY (ORCPT ); Tue, 28 Mar 2023 06:11:24 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 05AA683C2; Tue, 28 Mar 2023 03:11:02 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.98,297,1673881200"; d="scan'208";a="157440708" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 28 Mar 2023 19:10:50 +0900 Received: from localhost.localdomain (unknown [10.226.92.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 5326640071EC; Tue, 28 Mar 2023 19:10:47 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v7 09/10] pinctrl: renesas: rzg2l-poeg: output-disable request by external pin Date: Tue, 28 Mar 2023 11:10:10 +0100 Message-Id: <20230328101011.185594-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> References: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Add support for output-disable request by external pin. Signed-off-by: Biju Das --- drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 9 +++++++++ include/linux/pinctrl/rzg2l-poeg.h | 2 ++ 2 files changed, 11 insertions(+) diff --git a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c index 7576f756af3c..5d93a0be33f3 100644 --- a/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c +++ b/drivers/pinctrl/renesas/poeg/rzg2l-poeg.c @@ -15,13 +15,16 @@ #include #include #include +#include #include #include #include #define POEGG_IOCE BIT(5) +#define POEGG_PIDE BIT(4) #define POEGG_SSF BIT(3) #define POEGG_IOCF BIT(1) +#define POEGG_PIDF BIT(0) #define RZG2L_POEG_MAX_INDEX 3 @@ -113,6 +116,9 @@ static irqreturn_t rzg2l_poeg_irq(int irq, void *ptr) if (val & POEGG_IOCF) val &= ~POEGG_IOCF; + if (val & POEGG_PIDF) + val &= ~POEGG_PIDF; + rzg2l_poeg_write(chip, val); return IRQ_HANDLED; @@ -378,6 +384,9 @@ static int rzg2l_poeg_probe(struct platform_device *pdev) assign_bit(RZG2L_GPT_OABLF, chip->gpt_irq, true); assign_bit(RZG2L_GPT_DTEF, chip->gpt_irq, true); break; + case POEG_EXT_PIN_CTRL: + rzg2l_poeg_write(chip, POEGG_PIDE); + break; default: ret = -EINVAL; goto err_pm; diff --git a/include/linux/pinctrl/rzg2l-poeg.h b/include/linux/pinctrl/rzg2l-poeg.h index 5441de7f3751..359849fea6a0 100644 --- a/include/linux/pinctrl/rzg2l-poeg.h +++ b/include/linux/pinctrl/rzg2l-poeg.h @@ -7,11 +7,13 @@ #define RZG2L_GPT_DTEF 0 #define RZG2L_GPT_OABHF 1 #define RZG2L_GPT_OABLF 2 +#define RZG2L_POEG_EXT_PIN_CTRL 3 #define RZG2L_POEG_USR_CTRL_ENABLE_CMD 0 #define RZG2L_POEG_USR_CTRL_DISABLE_CMD 1 #define RZG2L_POEG_GPT_CFG_IRQ_CMD 2 #define RZG2L_POEG_GPT_FAULT_CLR_CMD 3 +#define RZG2L_POEG_EXT_PIN_CTRL_FAULT_CLR_CMD 4 struct poeg_event { __u32 gpt_disable_irq_status; From patchwork Tue Mar 28 10:10:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1762259 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4Pm57M4cvSz1yYS for ; Tue, 28 Mar 2023 21:11:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233014AbjC1KL0 (ORCPT ); Tue, 28 Mar 2023 06:11:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232725AbjC1KLU (ORCPT ); Tue, 28 Mar 2023 06:11:20 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2C6EE7D9A; Tue, 28 Mar 2023 03:10:59 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.98,297,1673881200"; d="scan'208";a="154049039" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 28 Mar 2023 19:10:53 +0900 Received: from localhost.localdomain (unknown [10.226.92.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id DB69640071F7; Tue, 28 Mar 2023 19:10:50 +0900 (JST) From: Biju Das To: Linus Walleij , Thierry Reding Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar Mahadev Lad Subject: [DO NOT APPLY PATCH v7 10/10] tools/poeg: Add test app for poeg Date: Tue, 28 Mar 2023 11:10:11 +0100 Message-Id: <20230328101011.185594-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> References: <20230328101011.185594-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Add test app for poeg Signed-off-by: Biju Das --- tools/poeg/Build | 1 + tools/poeg/Makefile | 53 ++++++++++++++++++++++ tools/poeg/poeg_app.c | 102 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 156 insertions(+) create mode 100644 tools/poeg/Build create mode 100644 tools/poeg/Makefile create mode 100644 tools/poeg/poeg_app.c diff --git a/tools/poeg/Build b/tools/poeg/Build new file mode 100644 index 000000000000..f960920a4afb --- /dev/null +++ b/tools/poeg/Build @@ -0,0 +1 @@ +poeg_app-y += poeg_app.o diff --git a/tools/poeg/Makefile b/tools/poeg/Makefile new file mode 100644 index 000000000000..669c914d9c98 --- /dev/null +++ b/tools/poeg/Makefile @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 +include ../scripts/Makefile.include + +bindir ?= /usr/bin + +ifeq ($(srctree),) +srctree := $(patsubst %/,%,$(dir $(CURDIR))) +srctree := $(patsubst %/,%,$(dir $(srctree))) +endif + +# Do not use make's built-in rules +# (this improves performance and avoids hard-to-debug behaviour); +MAKEFLAGS += -r + +override CFLAGS += -O2 -Wall -g -D_GNU_SOURCE -I$(OUTPUT)include + +ALL_TARGETS := poeg_app +ALL_PROGRAMS := $(patsubst %,$(OUTPUT)%,$(ALL_TARGETS)) + +all: $(ALL_PROGRAMS) + +export srctree OUTPUT CC LD CFLAGS +include $(srctree)/tools/build/Makefile.include + +# +# We need the following to be outside of kernel tree +# +$(OUTPUT)include/linux/poeg.h: ../../include/linux/pinctrl/rzg2l-poeg.h + mkdir -p $(OUTPUT)include/linux 2>&1 || true + ln -sf $(CURDIR)/../../include/linux/pinctrl/rzg2l-poeg.h $@ + +prepare: $(OUTPUT)include/linux/poeg.h + +POEG_EXAMPLE := $(OUTPUT)poeg_app.o +$(POEG_EXAMPLE): prepare FORCE + $(Q)$(MAKE) $(build)=poeg_app +$(OUTPUT)poeg_app: $(POEG_EXAMPLE) + $(QUIET_LINK)$(CC) $(CFLAGS) $(LDFLAGS) $< -o $@ + +clean: + rm -f $(ALL_PROGRAMS) + rm -rf $(OUTPUT)include/linux/poeg.h + find $(or $(OUTPUT),.) -name '*.o' -delete -o -name '\.*.d' -delete + +install: $(ALL_PROGRAMS) + install -d -m 755 $(DESTDIR)$(bindir); \ + for program in $(ALL_PROGRAMS); do \ + install $$program $(DESTDIR)$(bindir); \ + done + +FORCE: + +.PHONY: all install clean FORCE prepare diff --git a/tools/poeg/poeg_app.c b/tools/poeg/poeg_app.c new file mode 100644 index 000000000000..273ae1813e2f --- /dev/null +++ b/tools/poeg/poeg_app.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * POEG - example userspace application + * Copyright (C) 2023 Biju Das + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define USER_CTRL 1 +#define GPT_CTRL 0 +#define EXT_PIN_CTRL 0 + +int main(int argc, char *arg[]) +{ + struct poeg_cmd cmd; + int ret, fd; +#if GPT_CTRL + struct poeg_event event_data; + unsigned int val; + int i; +#endif + + fd = open("/dev/poeg3", O_RDWR); + if (fd < 0) + perror("open"); + else + printf("[POEG]open\n"); + +#if USER_CTRL + cmd.val = RZG2L_POEG_USR_CTRL_ENABLE_CMD; + cmd.channel = 4; + printf("[POEG] user control pin output disable enabled\n"); + ret = write(fd, &cmd, sizeof(cmd)); + if (ret == -1) { + perror("Failed to write cmd data"); + return 1; + } + sleep(3); + + printf("[POEG] user control pin output disable disabled\n"); + cmd.val = RZG2L_POEG_USR_CTRL_DISABLE_CMD; + cmd.channel = 4; + ret = write(fd, &cmd, sizeof(cmd)); + if (ret == -1) { + perror("Failed to write cmd data"); + return 1; + } +#endif + +#if GPT_CTRL + printf("[POEG] GPT control configure IRQ\n"); + cmd.val = RZG2L_POEG_GPT_CFG_IRQ_CMD; + cmd.channel = 4; + ret = write(fd, &cmd, sizeof(cmd)); + if (ret == -1) { + perror("Failed to write cmd data"); + return 1; + } + + for (;;) { + ret = read(fd, &event_data, sizeof(event_data)); + if (ret == -1) { + perror("Failed to read event data"); + return 1; + } + + val = event_data.gpt_disable_irq_status; + if (val) { + /* emulate fault clearing condition by adding delay */ + sleep(2); + for (i = 0; i < 8; i++) { + if (val & 7) { + printf("gpt ch:%u, irq=%x\n", i, val & 7); + cmd.val = RZG2L_POEG_GPT_FAULT_CLR_CMD; + cmd.channel = 4; + ret = write(fd, &cmd, sizeof(cmd)); + } + val >>= 3; + } + } + } +#endif + + if (close(fd) != 0) + perror("close"); + else + printf("[POEG]close\n"); + + return 0; +}