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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VI1EUR03FT044.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB7558 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tamar Christina via Gcc-patches From: Tamar Christina Reply-To: Tamar Christina Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi All, I previously made the test generic, but there's no list of targets that support integer MLA, and so it's not really feasible for me to make this generic. As such I've moved it to be AArch64 only. committed under the obvious rule. Thanks, Tamar gcc/testsuite/ChangeLog: PR testsuite/109118 * gcc.dg/mla_1.c: Moved to... * gcc.target/aarch64/sve/mla_3.c: ...here. --- inline copy of patch -- diff --git a/gcc/testsuite/gcc.dg/mla_1.c b/gcc/testsuite/gcc.target/aarch64/sve/mla_3.c similarity index 78% rename from gcc/testsuite/gcc.dg/mla_1.c rename to gcc/testsuite/gcc.target/aarch64/sve/mla_3.c index 98e5808ee7005e3e5c1b2d5688bfaf267a4d66ce..25e99f7d72a2fd5be0cdf9a8e9d9edddf22c40cb 100644 --- diff --git a/gcc/testsuite/gcc.dg/mla_1.c b/gcc/testsuite/gcc.target/aarch64/sve/mla_3.c similarity index 78% rename from gcc/testsuite/gcc.dg/mla_1.c rename to gcc/testsuite/gcc.target/aarch64/sve/mla_3.c index 98e5808ee7005e3e5c1b2d5688bfaf267a4d66ce..25e99f7d72a2fd5be0cdf9a8e9d9edddf22c40cb 100644 --- a/gcc/testsuite/gcc.dg/mla_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/mla_3.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target vect_int } */ -/* { dg-options "-O2 -msve-vector-bits=256 -march=armv8.2-a+sve -fdump-tree-optimized" { target aarch64*-*-* } } */ +/* { dg-options "-O2 -msve-vector-bits=256 -march=armv8.2-a+sve -fdump-tree-optimized" } */ unsigned int f1 (unsigned int a, unsigned int b, unsigned int c) { @@ -37,4 +36,4 @@ g3 (vec a, vec b, vec c) return a * b + c; } -/* { dg-final { scan-tree-dump-times {\.FMA } 1 "optimized" { target aarch64*-*-* } } } */ +/* { dg-final { scan-tree-dump-times {\.FMA } 1 "optimized" } } */ --- a/gcc/testsuite/gcc.dg/mla_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/mla_3.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target vect_int } */ -/* { dg-options "-O2 -msve-vector-bits=256 -march=armv8.2-a+sve -fdump-tree-optimized" { target aarch64*-*-* } } */ +/* { dg-options "-O2 -msve-vector-bits=256 -march=armv8.2-a+sve -fdump-tree-optimized" } */ unsigned int f1 (unsigned int a, unsigned int b, unsigned int c) { @@ -37,4 +36,4 @@ g3 (vec a, vec b, vec c) return a * b + c; } -/* { dg-final { scan-tree-dump-times {\.FMA } 1 "optimized" { target aarch64*-*-* } } } */ +/* { dg-final { scan-tree-dump-times {\.FMA } 1 "optimized" } } */