From patchwork Thu Mar 9 05:51:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 1754420 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=Srcn7o2d; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=BFBa2RxY; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:3::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PXJGW23Tlz246y for ; Thu, 9 Mar 2023 16:51:47 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4EYerPnigg1jK2UAtMXd4nUgCAj+F9hIvDjqe+KxQ7E=; b=Srcn7o2d84cg2a C6swZN7ep9GePt0PE43i4Zjl4kf93a6REoXCtEU5//SMOkpu29CVOXNGWEosRKN+8hQ3Ap6CbREMt PLtkuLTvwZ75byY5mwVGmARIDs3rVZzv+MEtS3DH86P/A9MFNOzHM9nsAYWphGSKHA72NszAXUqo/ eV53pIvK5fWhaEj1EQLA3Xkc3Zr4D1lqKKJ0SkIi1tFhmNjkl8KF2qX6lAuniN6Hg1B51PVEzz8Sh VlhvPyXFij1C0mFa1pegEFkwkv03KNeLQGWi9LxIVicPNW2tEYxx8V3A96u3lU5DRQweoQ8qFe0Ia Vw0MgDqqChUHcMMliWmg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pa9BX-007z27-Es; Thu, 09 Mar 2023 05:51:27 +0000 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pa9BU-007z0u-PO for opensbi@lists.infradead.org; Thu, 09 Mar 2023 05:51:26 +0000 Received: by mail-pj1-x102f.google.com with SMTP id l1so1124414pjt.2 for ; Wed, 08 Mar 2023 21:51:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678341081; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1dfhhsImxIYEVmMizOv/uXWCNaK4NjWRpPt5dV/S7Y8=; b=BFBa2RxYBa9qFzBtJav04nH+tjzv1Qu47r7ZAf5EJ5DTau3edglLQYbN5FokHTPOx9 8mNvd06/5cMs/Bwj+RV76Wbu77fqLy/8ycpBEkj/sWav/YwpCs29Eoh7b/0sMWOC569y Bd2FUNBmKO1kgKeWQRYz/GpuZEWLfrfOmVbU1DnmIqghIItMPqVR96i4YPlC41sF3atS u+0haCamoplVG+9T8XjGA063ngWwEaFf50mS958F90e16bM6LXTPbl8Z6qmLQGipn/Sj AaoePHY5Da8TeNomJRtNVnTdsuQc7UMx911I+o5hb0FeNJopQ3xGLkGRHkcU7gQPZ9IX jJrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678341081; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1dfhhsImxIYEVmMizOv/uXWCNaK4NjWRpPt5dV/S7Y8=; b=YD7BsBUwF2i9YadACr2ESaan6QJeClrf6Preb5L6ZHi/fxnv1v3CuQAxPbUx9ri4p0 YQYlZaoWzqLV7DtXWoINZk18m2mWGeS/vYZYUNIIBuXJn1kPOgGzWz4Cwhg/5tRZpl5t NVFApVCAYd21TZlreJiKrBN7crS9zvtClI1FyX8puLQLlB0walfPMf03H4pUvycNrnSD cNQwCC/+S6M4Ah4kbieQ6FOLqZnRIHlrB++S4r/Gi0NM/X58bkuez//BrTiDEBeSUdCR UIeMlekLER6CWysmwi9KYJu77zXTrOnyd3nrVJNePqEniKl4bcbU2EZFGrx+M0at+QBX sl6A== X-Gm-Message-State: AO0yUKXlvHr/EFqncOpOhGXju7VD2hbxVq/bXGx/sQHrMFn0iqQhMW9D FoJOU+t72Hidcx6EaLaoTn5HQ3u/kKvocr6Qw+7Itg== X-Google-Smtp-Source: AK7set8dXMgtCbYaf5XYypm/51SlXJa0b65FxcFKH8mJkfoiKxqxNmgdWyk2xakrG6aJ5Naz4om2FA== X-Received: by 2002:a17:902:a985:b0:19e:7f80:4165 with SMTP id bh5-20020a170902a98500b0019e7f804165mr16734138plb.17.1678341081416; Wed, 08 Mar 2023 21:51:21 -0800 (PST) Received: from mchitale-vm.. ([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id 13-20020a170902e9cd00b0019ac9c4f32esm10590724plk.309.2023.03.08.21.51.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 21:51:21 -0800 (PST) From: Mayuresh Chitale To: opensbi@lists.infradead.org Cc: Mayuresh Chitale , Atish Patra Subject: [PATCH v3 1/8] lib: sbi_pmu: add callback for counter width Date: Thu, 9 Mar 2023 11:21:05 +0530 Message-Id: <20230309055112.1516581-2-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230309055112.1516581-1-mchitale@ventanamicro.com> References: <20230309055112.1516581-1-mchitale@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230308_215124_843555_488B403A X-CRM114-Status: GOOD ( 11.61 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: This patch adds a callback to fetch the number of bits implemented for a custom firmware counter. If the callback fails or is not implemented then width defaults to 63. Signed-off-by: Mayuresh Chitale Reviewed-by: Atish Patra --- include/sbi/sbi_pmu.h | 5 +++++ lib/sbi/sbi_pmu.c | 6 ++++++ 2 files changed, 11 insertio [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:102f listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org This patch adds a callback to fetch the number of bits implemented for a custom firmware counter. If the callback fails or is not implemented then width defaults to 63. Signed-off-by: Mayuresh Chitale Reviewed-by: Atish Patra Reviewed-by: Anup Patel --- include/sbi/sbi_pmu.h | 5 +++++ lib/sbi/sbi_pmu.c | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h index c365243..b3b75c1 100644 --- a/include/sbi/sbi_pmu.h +++ b/include/sbi/sbi_pmu.h @@ -41,6 +41,11 @@ struct sbi_pmu_device { bool (*fw_counter_match_code)(uint32_t counter_index, uint32_t event_idx_code); + /** + * Fetch the max width of this counter in number of bits. + */ + int (*fw_counter_width)(void); + /** * Read value of custom firmware counter * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 154dbda..a99c045 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -761,6 +761,7 @@ unsigned long sbi_pmu_num_ctr(void) int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info) { + int width; union sbi_pmu_ctr_info cinfo = {0}; struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); @@ -782,6 +783,11 @@ int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info) cinfo.type = SBI_PMU_CTR_TYPE_FW; /* Firmware counters are always 64 bits wide */ cinfo.width = 63; + if (pmu_dev && pmu_dev->fw_counter_width) { + width = pmu_dev->fw_counter_width(); + if (width) + cinfo.width = width - 1; + } } *ctr_info = cinfo.value; From patchwork Thu Mar 9 05:51:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 1754421 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=zewGSsUk; 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([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id 13-20020a170902e9cd00b0019ac9c4f32esm10590724plk.309.2023.03.08.21.51.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 21:51:23 -0800 (PST) From: Mayuresh Chitale To: opensbi@lists.infradead.org Cc: Mayuresh Chitale , Atish Patra Subject: [PATCH v3 2/8] lib: sbi_pmu: Implement sbi_pmu_counter_fw_read_hi Date: Thu, 9 Mar 2023 11:21:06 +0530 Message-Id: <20230309055112.1516581-3-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230309055112.1516581-1-mchitale@ventanamicro.com> References: <20230309055112.1516581-1-mchitale@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230308_215127_131806_FB303EF0 X-CRM114-Status: UNSURE ( 9.88 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: To support 64 bit firmware counters on RV32 systems, we implement sbi_pmu_counter_fw_read_hi() which returns the upper 32 bits of the firmware counter value. On RV64 (or higher) systems, this function [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:629 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org To support 64 bit firmware counters on RV32 systems, we implement sbi_pmu_counter_fw_read_hi() which returns the upper 32 bits of the firmware counter value. On RV64 (or higher) systems, this function will always return zero. Signed-off-by: Mayuresh Chitale Reviewed-by: Atish Patra Reviewed-by: Anup Patel --- include/sbi/sbi_ecall_interface.h | 1 + lib/sbi/sbi_ecall_pmu.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h index 4c378c3..d448212 100644 --- a/include/sbi/sbi_ecall_interface.h +++ b/include/sbi/sbi_ecall_interface.h @@ -101,6 +101,7 @@ #define SBI_EXT_PMU_COUNTER_START 0x3 #define SBI_EXT_PMU_COUNTER_STOP 0x4 #define SBI_EXT_PMU_COUNTER_FW_READ 0x5 +#define SBI_EXT_PMU_COUNTER_FW_READ_HI 0x6 /** General pmu event codes specified in SBI PMU extension */ enum sbi_pmu_hw_generic_events_t { diff --git a/lib/sbi/sbi_ecall_pmu.c b/lib/sbi/sbi_ecall_pmu.c index 826c8a8..2d1e669 100644 --- a/lib/sbi/sbi_ecall_pmu.c +++ b/lib/sbi/sbi_ecall_pmu.c @@ -54,6 +54,14 @@ static int sbi_ecall_pmu_handler(unsigned long extid, unsigned long funcid, ret = sbi_pmu_ctr_fw_read(regs->a0, &temp); *out_val = temp; break; + case SBI_EXT_PMU_COUNTER_FW_READ_HI: +#if __riscv_xlen == 32 + ret = sbi_pmu_ctr_fw_read(regs->a0, &temp); + *out_val = temp >> 32 +#else + *out_val = 0; +#endif + break; case SBI_EXT_PMU_COUNTER_START: #if __riscv_xlen == 32 From patchwork Thu Mar 9 05:51:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 1754422 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=JTchRjhB; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=bcFeMpX+; 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X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: We reserve space for SBI implementation specific custom firmware events which can be used by M-mode firmwares and HS-mode hypervisors for their own use. This reserved space is intentionally large to e [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1033 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org We reserve space for SBI implementation specific custom firmware events which can be used by M-mode firmwares and HS-mode hypervisors for their own use. This reserved space is intentionally large to ensure that SBI implementation has enough space to accommodate platform specific firmware events as well. Signed-off-by: Mayuresh Chitale Reviewed-by: Atish Patra Reviewed-by: Anup Patel --- include/sbi/sbi_ecall_interface.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h index d448212..8d1cb97 100644 --- a/include/sbi/sbi_ecall_interface.h +++ b/include/sbi/sbi_ecall_interface.h @@ -185,6 +185,17 @@ enum sbi_pmu_fw_event_code_id { SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20, SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21, SBI_PMU_FW_MAX, + /* + * Event codes 22 to 255 are reserved for future use. + * Event codes 256 to 65534 are reserved for SBI implementation + * specific custom firmware events. + */ + SBI_PMU_FW_RESERVED_MAX = 0xFFFE, + /* + * Event code 0xFFFF is used for platform specific firmware + * events where the event data contains any event specific information. + */ + SBI_PMU_FW_PLATFORM = 0xFFFF, }; /** SBI PMU event idx type */ From patchwork Thu Mar 9 05:51:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 1754424 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id 13-20020a170902e9cd00b0019ac9c4f32esm10590724plk.309.2023.03.08.21.51.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 21:51:28 -0800 (PST) From: Mayuresh Chitale To: opensbi@lists.infradead.org Cc: Mayuresh Chitale Subject: [PATCH v3 4/8] lib: sbi_pmu: Rename fw_counter_value Date: Thu, 9 Mar 2023 11:21:08 +0530 Message-Id: <20230309055112.1516581-5-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230309055112.1516581-1-mchitale@ventanamicro.com> References: <20230309055112.1516581-1-mchitale@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230308_215132_419971_4D4B3644 X-CRM114-Status: GOOD ( 13.16 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Rename and reuse fw_counter_value arrary to save both the counter values for the SBI firmware events and event data for the SBI platform specific firmware events. Signed-off-by: Mayuresh Chitale --- lib/sbi/sbi_pmu.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:633 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Rename and reuse fw_counter_value arrary to save both the counter values for the SBI firmware events and event data for the SBI platform specific firmware events. Signed-off-by: Mayuresh Chitale Reviewed-by: Anup Patel Reviewed-by: Andrew Jones --- lib/sbi/sbi_pmu.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index a99c045..1a3c44d 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -65,8 +65,12 @@ static uint32_t active_events[SBI_HARTMASK_MAX_BITS][SBI_PMU_HW_CTR_MAX + SBI_PM #endif static unsigned long fw_counters_started[SBI_HARTMASK_MAX_BITS]; -/* Values of firmwares counters on each HART */ -static uint64_t fw_counters_value[SBI_HARTMASK_MAX_BITS][SBI_PMU_FW_CTR_MAX] = {0}; +/* + * Counter values for SBI firmware events and event codes for platform + * firmware events. Both are mutually exclusive and hence can optimally share + * the same memory. + */ +static uint64_t fw_counters_data[SBI_HARTMASK_MAX_BITS][SBI_PMU_FW_CTR_MAX] = {0}; /* Maximum number of hardware events available */ static uint32_t num_hw_events; @@ -185,10 +189,10 @@ int sbi_pmu_ctr_fw_read(uint32_t cidx, uint64_t *cval) if (SBI_PMU_FW_MAX <= event_code && pmu_dev && pmu_dev->fw_counter_read_value) - fw_counters_value[hartid][cidx - num_hw_ctrs] = + fw_counters_data[hartid][cidx - num_hw_ctrs] = pmu_dev->fw_counter_read_value(cidx - num_hw_ctrs); - *cval = fw_counters_value[hartid][cidx - num_hw_ctrs]; + *cval = fw_counters_data[hartid][cidx - num_hw_ctrs]; return 0; } @@ -372,7 +376,7 @@ static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code, } if (ival_update) - fw_counters_value[hartid][cidx - num_hw_ctrs] = ival; + fw_counters_data[hartid][cidx - num_hw_ctrs] = ival; fw_counters_started[hartid] |= BIT(cidx - num_hw_ctrs); return 0; @@ -711,13 +715,13 @@ skip_match: pmu_ctr_start_hw(ctr_idx, 0, false); } else if (event_type == SBI_PMU_EVENT_TYPE_FW) { if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE) - fw_counters_value[hartid][ctr_idx - num_hw_ctrs] = 0; + fw_counters_data[hartid][ctr_idx - num_hw_ctrs] = 0; if (flags & SBI_PMU_CFG_FLAG_AUTO_START) { if (SBI_PMU_FW_MAX <= event_code && pmu_dev && pmu_dev->fw_counter_start) { ret = pmu_dev->fw_counter_start( ctr_idx - num_hw_ctrs, event_code, - fw_counters_value[hartid][ctr_idx - num_hw_ctrs], + fw_counters_data[hartid][ctr_idx - num_hw_ctrs], true); if (ret) return ret; @@ -743,7 +747,7 @@ int sbi_pmu_ctr_incr_fw(enum sbi_pmu_fw_event_code_id fw_id) for (cidx = num_hw_ctrs; cidx < total_ctrs; cidx++) { if (get_cidx_code(active_events[hartid][cidx]) == fw_id && (fw_counters_started[hartid] & BIT(cidx - num_hw_ctrs))) { - fcounter = &fw_counters_value[hartid][cidx - num_hw_ctrs]; + fcounter = &fw_counters_data[hartid][cidx - num_hw_ctrs]; break; } } @@ -803,7 +807,7 @@ static void pmu_reset_event_map(u32 hartid) for (j = 3; j < total_ctrs; j++) active_events[hartid][j] = SBI_PMU_EVENT_IDX_INVALID; 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([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id 13-20020a170902e9cd00b0019ac9c4f32esm10590724plk.309.2023.03.08.21.51.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 21:51:30 -0800 (PST) From: Mayuresh Chitale To: opensbi@lists.infradead.org Cc: Mayuresh Chitale Subject: [PATCH v3 5/8] lib: sbi_pmu: Update sbi_pmu dev ops Date: Thu, 9 Mar 2023 11:21:09 +0530 Message-Id: <20230309055112.1516581-6-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230309055112.1516581-1-mchitale@ventanamicro.com> References: <20230309055112.1516581-1-mchitale@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230308_215133_940461_BA0F1611 X-CRM114-Status: GOOD ( 15.81 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Update fw_event_validate_code, fw_counter_match_code and fw_counter_start ops which used a 32 bit event code to use the 64 bit event data instead. Signed-off-by: Mayuresh Chitale --- include/sbi/sbi_pmu.h | 9 ++++----- lib/sbi/sbi_pmu.c | 30 +++++++++++++++++ 2 files changed, 21 insertions(+), 18 deletion [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1029 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Update fw_event_validate_code, fw_counter_match_code and fw_counter_start ops which used a 32 bit event code to use the 64 bit event data instead. Signed-off-by: Mayuresh Chitale Reviewed-by: Anup Patel --- include/sbi/sbi_pmu.h | 9 ++++----- lib/sbi/sbi_pmu.c | 30 +++++++++++++++++------------- 2 files changed, 21 insertions(+), 18 deletions(-) diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h index b3b75c1..3232e14 100644 --- a/include/sbi/sbi_pmu.h +++ b/include/sbi/sbi_pmu.h @@ -30,16 +30,15 @@ struct sbi_pmu_device { /** * Validate event code of custom firmware event - * Note: SBI_PMU_FW_MAX <= event_idx_code */ - int (*fw_event_validate_code)(uint32_t event_idx_code); + int (*fw_event_validate_encoding)(uint64_t event_data); /** * Match custom firmware counter with custom firmware event * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX */ - bool (*fw_counter_match_code)(uint32_t counter_index, - uint32_t event_idx_code); + bool (*fw_counter_match_encoding)(uint32_t counter_index, + uint64_t event_data); /** * Fetch the max width of this counter in number of bits. @@ -58,7 +57,7 @@ struct sbi_pmu_device { * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX */ int (*fw_counter_start)(uint32_t counter_index, - uint32_t event_idx_code, + uint64_t event_data, uint64_t init_val, bool init_val_update); /** diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 1a3c44d..1169ef2 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -110,7 +110,7 @@ static bool pmu_event_select_overlap(struct sbi_pmu_hw_event *evt, return false; } -static int pmu_event_validate(unsigned long event_idx) +static int pmu_event_validate(unsigned long event_idx, uint64_t edata) { uint32_t event_idx_type = get_cidx_type(event_idx); uint32_t event_idx_code = get_cidx_code(event_idx); @@ -123,8 +123,8 @@ static int pmu_event_validate(unsigned long event_idx) break; case SBI_PMU_EVENT_TYPE_FW: if (SBI_PMU_FW_MAX <= event_idx_code && - pmu_dev && pmu_dev->fw_event_validate_code) - return pmu_dev->fw_event_validate_code(event_idx_code); + pmu_dev && pmu_dev->fw_event_validate_encoding) + return pmu_dev->fw_event_validate_encoding(edata); else event_idx_code_max = SBI_PMU_FW_MAX; break; @@ -361,7 +361,8 @@ int sbi_pmu_irq_bit(void) } static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code, - uint64_t ival, bool ival_update) + uint64_t event_data, uint64_t ival, + bool ival_update) { int ret; u32 hartid = current_hartid(); @@ -369,7 +370,7 @@ static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code, if (SBI_PMU_FW_MAX <= event_code && pmu_dev && pmu_dev->fw_counter_start) { ret = pmu_dev->fw_counter_start(cidx - num_hw_ctrs, - event_code, + event_data, ival, ival_update); if (ret) return ret; @@ -390,6 +391,7 @@ int sbi_pmu_ctr_start(unsigned long cbase, unsigned long cmask, int ret = SBI_EINVAL; bool bUpdate = false; int i, cidx; + uint64_t edata = 0; if ((cbase + sbi_fls(cmask)) >= total_ctrs) return ret; @@ -404,7 +406,8 @@ int sbi_pmu_ctr_start(unsigned long cbase, unsigned long cmask, /* Continue the start operation for other counters */ continue; else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW) - ret = pmu_ctr_start_fw(cidx, event_code, ival, bUpdate); + ret = pmu_ctr_start_fw(cidx, event_code, edata, ival, + bUpdate); else ret = pmu_ctr_start_hw(cidx, ival, bUpdate); } @@ -644,7 +647,7 @@ static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, unsigned lo * check. */ static int pmu_ctr_find_fw(unsigned long cbase, unsigned long cmask, - uint32_t event_code, u32 hartid) + uint32_t event_code, u32 hartid, uint64_t edata) { int i, cidx; @@ -655,9 +658,9 @@ static int pmu_ctr_find_fw(unsigned long cbase, unsigned long cmask, if (active_events[hartid][i] != SBI_PMU_EVENT_IDX_INVALID) continue; if (SBI_PMU_FW_MAX <= event_code && - pmu_dev && pmu_dev->fw_counter_match_code) { - if (!pmu_dev->fw_counter_match_code(cidx - num_hw_ctrs, - event_code)) + pmu_dev && pmu_dev->fw_counter_match_encoding) { + if (!pmu_dev->fw_counter_match_encoding(cidx - num_hw_ctrs, + edata)) continue; } @@ -679,7 +682,7 @@ int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask, if ((cidx_base + sbi_fls(cidx_mask)) >= total_ctrs) return SBI_EINVAL; - event_type = pmu_event_validate(event_idx); + event_type = pmu_event_validate(event_idx, event_data); if (event_type < 0) return SBI_EINVAL; event_code = get_cidx_code(event_idx); @@ -697,7 +700,8 @@ int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask, if (event_type == SBI_PMU_EVENT_TYPE_FW) { /* Any firmware counter can be used track any firmware event */ - ctr_idx = pmu_ctr_find_fw(cidx_base, cidx_mask, event_code, hartid); + ctr_idx = pmu_ctr_find_fw(cidx_base, cidx_mask, event_code, + hartid, event_data); } else { ctr_idx = pmu_ctr_find_hw(cidx_base, cidx_mask, flags, event_idx, event_data); @@ -720,7 +724,7 @@ skip_match: if (SBI_PMU_FW_MAX <= event_code && pmu_dev && pmu_dev->fw_counter_start) { ret = pmu_dev->fw_counter_start( - ctr_idx - num_hw_ctrs, event_code, + ctr_idx - num_hw_ctrs, event_data, fw_counters_data[hartid][ctr_idx - num_hw_ctrs], true); if (ret) From patchwork Thu Mar 9 05:51:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 1754423 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; 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([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id 13-20020a170902e9cd00b0019ac9c4f32esm10590724plk.309.2023.03.08.21.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 21:51:32 -0800 (PST) From: Mayuresh Chitale To: opensbi@lists.infradead.org Cc: Mayuresh Chitale Subject: [PATCH v3 6/8] lib: sbi_pmu: Use dedicated event code for platform firmware events Date: Thu, 9 Mar 2023 11:21:10 +0530 Message-Id: <20230309055112.1516581-7-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230309055112.1516581-1-mchitale@ventanamicro.com> References: <20230309055112.1516581-1-mchitale@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230308_215133_648686_CD93A7E2 X-CRM114-Status: GOOD ( 16.51 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: For all platform specific firmware event operations use the dedicated event code (0xFFFF) when matching against the input firmware event. Furthermore save the real platform specific firmware event cod [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:102f listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org For all platform specific firmware event operations use the dedicated event code (0xFFFF) when matching against the input firmware event. Furthermore save the real platform specific firmware event code received as the event data for future use. Signed-off-by: Mayuresh Chitale Reviewed-by: Anup Patel --- lib/sbi/sbi_pmu.c | 65 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 52 insertions(+), 13 deletions(-) diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 1169ef2..d083198 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -122,7 +122,12 @@ static int pmu_event_validate(unsigned long event_idx, uint64_t edata) event_idx_code_max = SBI_PMU_HW_GENERAL_MAX; break; case SBI_PMU_EVENT_TYPE_FW: - if (SBI_PMU_FW_MAX <= event_idx_code && + if ((event_idx_code >= SBI_PMU_FW_MAX && + event_idx_code <= SBI_PMU_FW_RESERVED_MAX) || + event_idx_code > SBI_PMU_FW_PLATFORM) + return SBI_EINVAL; + + if (SBI_PMU_FW_PLATFORM == event_idx_code && pmu_dev && pmu_dev->fw_event_validate_encoding) return pmu_dev->fw_event_validate_encoding(edata); else @@ -187,12 +192,19 @@ int sbi_pmu_ctr_fw_read(uint32_t cidx, uint64_t *cval) if (event_idx_type != SBI_PMU_EVENT_TYPE_FW) return SBI_EINVAL; - if (SBI_PMU_FW_MAX <= event_code && - pmu_dev && pmu_dev->fw_counter_read_value) - fw_counters_data[hartid][cidx - num_hw_ctrs] = - pmu_dev->fw_counter_read_value(cidx - num_hw_ctrs); + if ((event_code >= SBI_PMU_FW_MAX && + event_code <= SBI_PMU_FW_RESERVED_MAX) || + event_code > SBI_PMU_FW_PLATFORM) + return SBI_EINVAL; - *cval = fw_counters_data[hartid][cidx - num_hw_ctrs]; + if (SBI_PMU_FW_PLATFORM == event_code) { + if (pmu_dev && pmu_dev->fw_counter_read_value) + *cval = pmu_dev->fw_counter_read_value(cidx - + num_hw_ctrs); + else + *cval = 0; + } else + *cval = fw_counters_data[hartid][cidx - num_hw_ctrs]; return 0; } @@ -367,8 +379,17 @@ static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code, int ret; u32 hartid = current_hartid(); - if (SBI_PMU_FW_MAX <= event_code && - pmu_dev && pmu_dev->fw_counter_start) { + if ((event_code >= SBI_PMU_FW_MAX && + event_code <= SBI_PMU_FW_RESERVED_MAX) || + event_code > SBI_PMU_FW_PLATFORM) + return SBI_EINVAL; + + if (SBI_PMU_FW_PLATFORM == event_code) { + if (!pmu_dev || + !pmu_dev->fw_counter_start) { + return SBI_EINVAL; + } + ret = pmu_dev->fw_counter_start(cidx - num_hw_ctrs, event_data, ival, ival_update); @@ -386,12 +407,13 @@ static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code, int sbi_pmu_ctr_start(unsigned long cbase, unsigned long cmask, unsigned long flags, uint64_t ival) { + u32 hartid = current_hartid(); int event_idx_type; uint32_t event_code; int ret = SBI_EINVAL; bool bUpdate = false; int i, cidx; - uint64_t edata = 0; + uint64_t edata; if ((cbase + sbi_fls(cmask)) >= total_ctrs) return ret; @@ -405,9 +427,13 @@ int sbi_pmu_ctr_start(unsigned long cbase, unsigned long cmask, if (event_idx_type < 0) /* Continue the start operation for other counters */ continue; - else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW) + else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW) { + edata = (event_code == SBI_PMU_FW_PLATFORM) ? + fw_counters_data[hartid][cidx - num_hw_ctrs] + : 0x0; ret = pmu_ctr_start_fw(cidx, event_code, edata, ival, bUpdate); + } else ret = pmu_ctr_start_hw(cidx, ival, bUpdate); } @@ -441,7 +467,12 @@ static int pmu_ctr_stop_fw(uint32_t cidx, uint32_t event_code) { int ret; - if (SBI_PMU_FW_MAX <= event_code && + if ((event_code >= SBI_PMU_FW_MAX && + event_code <= SBI_PMU_FW_RESERVED_MAX) || + event_code > SBI_PMU_FW_PLATFORM) + return SBI_EINVAL; + + if (SBI_PMU_FW_PLATFORM == event_code && pmu_dev && pmu_dev->fw_counter_stop) { ret = pmu_dev->fw_counter_stop(cidx - num_hw_ctrs); if (ret) @@ -651,13 +682,18 @@ static int pmu_ctr_find_fw(unsigned long cbase, unsigned long cmask, { int i, cidx; + if ((event_code >= SBI_PMU_FW_MAX && + event_code <= SBI_PMU_FW_RESERVED_MAX) || + event_code > SBI_PMU_FW_PLATFORM) + return SBI_EINVAL; + for_each_set_bit(i, &cmask, BITS_PER_LONG) { cidx = i + cbase; if (cidx < num_hw_ctrs || total_ctrs <= cidx) continue; if (active_events[hartid][i] != SBI_PMU_EVENT_IDX_INVALID) continue; - if (SBI_PMU_FW_MAX <= event_code && + if (SBI_PMU_FW_PLATFORM == event_code && pmu_dev && pmu_dev->fw_counter_match_encoding) { if (!pmu_dev->fw_counter_match_encoding(cidx - num_hw_ctrs, edata)) @@ -702,6 +738,9 @@ int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask, /* Any firmware counter can be used track any firmware event */ ctr_idx = pmu_ctr_find_fw(cidx_base, cidx_mask, event_code, hartid, event_data); + if (event_code == SBI_PMU_FW_PLATFORM) + fw_counters_data[hartid][ctr_idx - num_hw_ctrs] = + event_data; } else { ctr_idx = pmu_ctr_find_hw(cidx_base, cidx_mask, flags, event_idx, event_data); @@ -721,7 +760,7 @@ skip_match: if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE) fw_counters_data[hartid][ctr_idx - num_hw_ctrs] = 0; if (flags & SBI_PMU_CFG_FLAG_AUTO_START) { - if (SBI_PMU_FW_MAX <= event_code && + if (SBI_PMU_FW_PLATFORM == event_code && pmu_dev && pmu_dev->fw_counter_start) { ret = pmu_dev->fw_counter_start( ctr_idx - num_hw_ctrs, event_data, From patchwork Thu Mar 9 05:51:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 1754426 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Add fw_counter_write_value API for platform specific firmware events which separates setting the counter's initial value from starting the counter. This is required so that the fw_event_data array can [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:632 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Add fw_counter_write_value API for platform specific firmware events which separates setting the counter's initial value from starting the counter. This is required so that the fw_event_data array can be reused to save the event data received. Signed-off-by: Mayuresh Chitale Reviewed-by: Anup Patel --- include/sbi/sbi_pmu.h | 11 ++++++++--- lib/sbi/sbi_pmu.c | 25 +++++++++++++------------ 2 files changed, 21 insertions(+), 15 deletions(-) diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h index 3232e14..53f2700 100644 --- a/include/sbi/sbi_pmu.h +++ b/include/sbi/sbi_pmu.h @@ -51,14 +51,19 @@ struct sbi_pmu_device { */ uint64_t (*fw_counter_read_value)(uint32_t counter_index); + /** + * Write value to custom firmware counter + * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX + */ + void (*fw_counter_write_value)(uint32_t counter_index, + uint64_t value); + /** * Start custom firmware counter - * Note: SBI_PMU_FW_MAX <= event_idx_code * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX */ int (*fw_counter_start)(uint32_t counter_index, - uint64_t event_data, - uint64_t init_val, bool init_val_update); + uint64_t event_data); /** * Stop custom firmware counter diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index d083198..00a2c3e 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -376,7 +376,6 @@ static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code, uint64_t event_data, uint64_t ival, bool ival_update) { - int ret; u32 hartid = current_hartid(); if ((event_code >= SBI_PMU_FW_MAX && @@ -386,19 +385,22 @@ static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code, if (SBI_PMU_FW_PLATFORM == event_code) { if (!pmu_dev || + !pmu_dev->fw_counter_write_value || !pmu_dev->fw_counter_start) { return SBI_EINVAL; } - ret = pmu_dev->fw_counter_start(cidx - num_hw_ctrs, - event_data, - ival, ival_update); - if (ret) - return ret; + if (ival_update) + pmu_dev->fw_counter_write_value(cidx - num_hw_ctrs, + ival); + + return pmu_dev->fw_counter_start(cidx - num_hw_ctrs, + event_data); + } else { + if (ival_update) + fw_counters_data[hartid][cidx - num_hw_ctrs] = ival; } - if (ival_update) - fw_counters_data[hartid][cidx - num_hw_ctrs] = ival; fw_counters_started[hartid] |= BIT(cidx - num_hw_ctrs); return 0; @@ -762,10 +764,9 @@ skip_match: if (flags & SBI_PMU_CFG_FLAG_AUTO_START) { if (SBI_PMU_FW_PLATFORM == event_code && pmu_dev && pmu_dev->fw_counter_start) { - ret = pmu_dev->fw_counter_start( - ctr_idx - num_hw_ctrs, event_data, - fw_counters_data[hartid][ctr_idx - num_hw_ctrs], - true); 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([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id 13-20020a170902e9cd00b0019ac9c4f32esm10590724plk.309.2023.03.08.21.51.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 21:51:37 -0800 (PST) From: Mayuresh Chitale To: opensbi@lists.infradead.org Cc: Mayuresh Chitale , Atish Patra Subject: [PATCH v3 8/8] lib: sbi_pmu: Add hartid parameter PMU device ops Date: Thu, 9 Mar 2023 11:21:12 +0530 Message-Id: <20230309055112.1516581-9-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230309055112.1516581-1-mchitale@ventanamicro.com> References: <20230309055112.1516581-1-mchitale@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230308_215141_633413_0B9F788F X-CRM114-Status: GOOD ( 12.48 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Platform specific firmware event handler may leverage the hartid to program per hart specific registers for a given counter. Signed-off-by: Mayuresh Chitale Reviewed-by: Atish Patra --- include/sbi/sbi_pmu.h | 14 ++++++++------ lib/sbi/sbi_pmu.c | 25 +++++++++++++++--------- [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:62c listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Platform specific firmware event handler may leverage the hartid to program per hart specific registers for a given counter. Signed-off-by: Mayuresh Chitale Reviewed-by: Atish Patra Reviewed-by: Anup Patel --- include/sbi/sbi_pmu.h | 14 ++++++++------ lib/sbi/sbi_pmu.c | 25 +++++++++++++++---------- 2 files changed, 23 insertions(+), 16 deletions(-) diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h index 53f2700..16f6877 100644 --- a/include/sbi/sbi_pmu.h +++ b/include/sbi/sbi_pmu.h @@ -31,13 +31,14 @@ struct sbi_pmu_device { /** * Validate event code of custom firmware event */ - int (*fw_event_validate_encoding)(uint64_t event_data); + int (*fw_event_validate_encoding)(uint32_t hartid, uint64_t event_data); /** * Match custom firmware counter with custom firmware event * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX */ - bool (*fw_counter_match_encoding)(uint32_t counter_index, + bool (*fw_counter_match_encoding)(uint32_t hartid, + uint32_t counter_index, uint64_t event_data); /** @@ -49,27 +50,28 @@ struct sbi_pmu_device { * Read value of custom firmware counter * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX */ - uint64_t (*fw_counter_read_value)(uint32_t counter_index); + uint64_t (*fw_counter_read_value)(uint32_t hartid, + uint32_t counter_index); /** * Write value to custom firmware counter * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX */ - void (*fw_counter_write_value)(uint32_t counter_index, + void (*fw_counter_write_value)(uint32_t hartid, uint32_t counter_index, uint64_t value); /** * Start custom firmware counter * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX */ - int (*fw_counter_start)(uint32_t counter_index, + int (*fw_counter_start)(uint32_t hartid, uint32_t counter_index, uint64_t event_data); /** * Stop custom firmware counter * Note: 0 <= counter_index < SBI_PMU_FW_CTR_MAX */ - int (*fw_counter_stop)(uint32_t counter_index); + int (*fw_counter_stop)(uint32_t hartid, uint32_t counter_index); /** * Custom enable irq for hardware counter diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 00a2c3e..74d6912 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -116,6 +116,7 @@ static int pmu_event_validate(unsigned long event_idx, uint64_t edata) uint32_t event_idx_code = get_cidx_code(event_idx); uint32_t event_idx_code_max = -1; uint32_t cache_ops_result, cache_ops_id, cache_id; + u32 hartid = current_hartid(); switch(event_idx_type) { case SBI_PMU_EVENT_TYPE_HW: @@ -129,7 +130,8 @@ static int pmu_event_validate(unsigned long event_idx, uint64_t edata) if (SBI_PMU_FW_PLATFORM == event_idx_code && pmu_dev && pmu_dev->fw_event_validate_encoding) - return pmu_dev->fw_event_validate_encoding(edata); + return pmu_dev->fw_event_validate_encoding(hartid, + edata); else event_idx_code_max = SBI_PMU_FW_MAX; break; @@ -199,7 +201,8 @@ int sbi_pmu_ctr_fw_read(uint32_t cidx, uint64_t *cval) if (SBI_PMU_FW_PLATFORM == event_code) { if (pmu_dev && pmu_dev->fw_counter_read_value) - *cval = pmu_dev->fw_counter_read_value(cidx - + *cval = pmu_dev->fw_counter_read_value(hartid, + cidx - num_hw_ctrs); else *cval = 0; @@ -391,10 +394,11 @@ static int pmu_ctr_start_fw(uint32_t cidx, uint32_t event_code, } if (ival_update) - pmu_dev->fw_counter_write_value(cidx - num_hw_ctrs, + pmu_dev->fw_counter_write_value(hartid, + cidx - num_hw_ctrs, ival); - return pmu_dev->fw_counter_start(cidx - num_hw_ctrs, + return pmu_dev->fw_counter_start(hartid, cidx - num_hw_ctrs, event_data); } else { if (ival_update) @@ -467,6 +471,7 @@ static int pmu_ctr_stop_hw(uint32_t cidx) static int pmu_ctr_stop_fw(uint32_t cidx, uint32_t event_code) { + u32 hartid = current_hartid(); int ret; if ((event_code >= SBI_PMU_FW_MAX && @@ -476,7 +481,7 @@ static int pmu_ctr_stop_fw(uint32_t cidx, uint32_t event_code) if (SBI_PMU_FW_PLATFORM == event_code && pmu_dev && pmu_dev->fw_counter_stop) { - ret = pmu_dev->fw_counter_stop(cidx - num_hw_ctrs); + ret = pmu_dev->fw_counter_stop(hartid, cidx - num_hw_ctrs); if (ret) return ret; } @@ -697,8 +702,9 @@ static int pmu_ctr_find_fw(unsigned long cbase, unsigned long cmask, continue; if (SBI_PMU_FW_PLATFORM == event_code && pmu_dev && pmu_dev->fw_counter_match_encoding) { - if (!pmu_dev->fw_counter_match_encoding(cidx - num_hw_ctrs, - edata)) + if (!pmu_dev->fw_counter_match_encoding(hartid, + cidx - num_hw_ctrs, + edata)) continue; } @@ -764,9 +770,8 @@ skip_match: if (flags & SBI_PMU_CFG_FLAG_AUTO_START) { if (SBI_PMU_FW_PLATFORM == event_code && pmu_dev && pmu_dev->fw_counter_start) { - ret = pmu_dev->fw_counter_start(ctr_idx - - num_hw_ctrs, - event_data); + ret = pmu_dev->fw_counter_start(hartid, + ctr_idx - num_hw_ctrs, event_data); if (ret) return ret; }