From patchwork Thu Mar 2 14:10:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamlesh Gurudasani X-Patchwork-Id: 1750754 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=rCn+404Y; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PSCjG5QJ0z1yWy for ; Fri, 3 Mar 2023 01:12:18 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9B8C085C81; Thu, 2 Mar 2023 15:12:11 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="rCn+404Y"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 62F4085C75; Thu, 2 Mar 2023 15:12:10 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1F86985C70 for ; Thu, 2 Mar 2023 15:12:08 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=kamlesh@ti.com Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 322EC67q001122 for ; Thu, 2 Mar 2023 08:12:06 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1677766326; bh=ezWrNkUs9AnBo9Y3WJvG4Q5hOwEHeg/cCW8dePbG6II=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rCn+404YBrGenZ1QOuiLD7WRbE3D4UjLuk9LaUIr/QrE5fFO2QiEJ9kBuI+TBzXgQ EYKRkrYW+tKnLGBUb6EZ2PpWXybsZoQXMGMS03Hy+dClNRrKevAaclgbPwoPd0AvoN TD2hjiZSXz6q/dXueGTJxeh1HlI7UHpwBqmCqFrQ= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 322EC6xg030710 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Thu, 2 Mar 2023 08:12:06 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 2 Mar 2023 08:12:06 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 2 Mar 2023 08:12:06 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 322EC5qp007715; Thu, 2 Mar 2023 08:12:05 -0600 From: To: CC: Kamlesh Gurudasani Subject: [PATCH 1/2] arm: mach-k3: am62: move scratch board area to HSM RAM Date: Thu, 2 Mar 2023 19:40:46 +0530 Message-ID: <20230302141047.3175114-2-kamlesh@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302141047.3175114-1-kamlesh@ti.com> References: <20230302141047.3175114-1-kamlesh@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Kamlesh Gurudasani On high security devices, ROM enables firewalls to protect the OCSRAM region access during bootup. Only after TIFS has started (and had time to disable the OCSRAM firewall region) will we have write access to the region. So, move scratch board area to HSM RAM. Signed-off-by: Kamlesh Gurudasani --- arch/arm/mach-k3/include/mach/am62_hardware.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index 17d3228cba..db4a32cd46 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -55,7 +55,6 @@ #define ROM_EXTENDED_BOOT_DATA_INFO 0x43c3f1e0 -/* Use Last 2K as Scratch pad */ -#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x70000000 +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000 #endif /* __ASM_ARCH_AM62_HARDWARE_H */ From patchwork Thu Mar 2 14:10:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamlesh Gurudasani X-Patchwork-Id: 1750755 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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spf=pass smtp.mailfrom=kamlesh@ti.com Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 322EC9ja001138 for ; Thu, 2 Mar 2023 08:12:09 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1677766329; bh=lKRfKETlug3siCDFIbSEcNr2vX5hSCTu1Mq/bOounlw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qJ20TWH5JrLcjUqx+7HMOGhTVcgCV5w7jtQ8PgSFVmcG2Y/tQ1dVDJReVLmQe+ESh jATE4KPlItZQwPVAhvkW+ZoMumce1KlUux4st5IqAlJsr8HFDqW4x7n/8wqNXVIlt8 FanvC0Q+8tRKU7caxxELafHtaWlDQQa8qgtGkxG8= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 322EC96D030735 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Thu, 2 Mar 2023 08:12:09 -0600 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 2 Mar 2023 08:12:08 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 2 Mar 2023 08:12:09 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 322EC8QQ056258; Thu, 2 Mar 2023 08:12:08 -0600 From: To: CC: Kamlesh Gurudasani Subject: [PATCH 2/2] configs: am62: move stack and heap to HSM RAM Date: Thu, 2 Mar 2023 19:40:47 +0530 Message-ID: <20230302141047.3175114-3-kamlesh@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230302141047.3175114-1-kamlesh@ti.com> References: <20230302141047.3175114-1-kamlesh@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Kamlesh Gurudasani On high security devices, ROM enables firewalls to protect the OCSRAM region access during bootup. Only after TIFS has started (and had time to disable the OCSRAM firewall region) will we have write access to the region. This means we will need to move the stack & heap from OCSRAM to HSM RAM and reduce the size of BSS and the SPL to allow it to fit properly. To protect us from overflowing our ~256k of HSM SRAM, add limits and check during the wakeup SPL build. Signed-off-by: Kamlesh Gurudasani --- configs/am62x_evm_r5_defconfig | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index 4f9ecf2661..44a9130d99 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -8,7 +8,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM625=y CONFIG_TARGET_AM625_R5_EVM=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7000ffff +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0 CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y @@ -19,7 +19,9 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 -CONFIG_SPL_SIZE_LIMIT=0x40000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000 +CONFIG_SPL_SIZE_LIMIT=0x3A7F0 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -28,10 +30,14 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_MAX_SIZE=0x3B000 +CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x43c37800 -CONFIG_SPL_BSS_MAX_SIZE=0x5000 +CONFIG_SPL_BSS_START_ADDR=0x43c3b000 +CONFIG_SPL_BSS_MAX_SIZE=0x3000 +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y