From patchwork Fri Mar 16 18:54:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vladimir Makarov X-Patchwork-Id: 887103 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-474875-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="qfxSXU4q"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 402vlZ1x4gz9sPk for ; Sat, 17 Mar 2018 05:54:48 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=So+nPAYZAC1bPJap2UVQp33RxoaIhnkmGGVeRqN2UQZAJ2JOlh MS1NgcRNk7Pt1wo+jPLtRMb0vAmg+Bd5jgYZLi26WJVoGNOUuoIMTAMzk40BYK/A Qd39Dq/jJnkI/ncgzD5WzrxDU15NsNy8saByUC2oUSD4CVDJnbuGpCDmw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=j6Q98rYv64kfaqRdMCedfSvB7s8=; b=qfxSXU4q3LmbMk5+bk6Z SPyjKYDhOcme7Kg/v/+mjRfGicTRkAytIT5VBKxU1GMhXCTQApIF+He2QgvC0dwj JDfrfXWaXT3mM3bJWt81f6CKkaloVohJq/3LBCQng0qgnbnHtMLsQxTVjsCi3T9K a62HRXZqqH5CyNP62aCP5WU= Received: (qmail 43677 invoked by alias); 16 Mar 2018 18:54:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 43662 invoked by uid 89); 16 Mar 2018 18:54:41 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-10.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_NUMSUBJECT, KAM_SHORT, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy= X-HELO: mx1.redhat.com Received: from mx3-rdu2.redhat.com (HELO mx1.redhat.com) (66.187.233.73) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 16 Mar 2018 18:54:39 +0000 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 42EFD40201A3 for ; Fri, 16 Mar 2018 18:54:28 +0000 (UTC) Received: from [10.10.120.42] (ovpn-120-42.rdu2.redhat.com [10.10.120.42]) by smtp.corp.redhat.com (Postfix) with ESMTP id 08D1C10B00B1 for ; Fri, 16 Mar 2018 18:54:27 +0000 (UTC) To: "gcc-patches@gcc.gnu.org" From: Vladimir Makarov Subject: patch to fix PR84876 Message-ID: <78806caf-f7be-e0b3-9b06-64df853b26f3@redhat.com> Date: Fri, 16 Mar 2018 14:54:27 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 X-IsSubscribed: yes The following patch fixes   https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84876 and another problem with LRA cycling which occurred on the same test. The patch was successfully bootstrapped and tested on i686 and x86_64. Committed as rev. 258602. Index: ChangeLog =================================================================== --- ChangeLog (revision 258601) +++ ChangeLog (working copy) @@ -1,3 +1,11 @@ +2018-03-16 Vladimir Makarov + + PR target/84876 + * lra-assigns.c (lra_split_hard_reg_for): Don't use + regno_allocno_class_array and sorted_pseudos. + * lra-constraints.c (spill_hard_reg_in_range): Ignore hard regs in + insns where regno is used. + 2018-03-16 Martin Liska PR ipa/84833 Index: testsuite/ChangeLog =================================================================== --- testsuite/ChangeLog (revision 258601) +++ testsuite/ChangeLog (working copy) @@ -1,3 +1,8 @@ +2018-03-16 Vladimir Makarov + + PR target/84876 + * gcc.target/i386/pr84876.c: New test. + 2018-03-16 Martin Liska PR ipa/84833 Index: lra-assigns.c =================================================================== --- lra-assigns.c (revision 258504) +++ lra-assigns.c (working copy) @@ -1737,41 +1737,46 @@ find_reload_regno_insns (int regno, rtx_ bool lra_split_hard_reg_for (void) { - int i, regno, n; + int i, regno; rtx_insn *insn, *first, *last; unsigned int u; bitmap_iterator bi; + enum reg_class rclass; int max_regno = max_reg_num (); /* We did not assign hard regs to reload pseudos after two iterations. Either it's an asm and something is wrong with the constraints, or we have run out of spill registers; error out in either case. */ bool asm_p = false; - bitmap_head failed_reload_insns; + bitmap_head failed_reload_insns, failed_reload_pseudos; if (lra_dump_file != NULL) fprintf (lra_dump_file, "\n****** Splitting a hard reg after assignment #%d: ******\n\n", lra_assignment_iter); - for (n = 0, i = lra_constraint_new_regno_start; i < max_regno; i++) + bitmap_initialize (&failed_reload_pseudos, ®_obstack); + for (i = lra_constraint_new_regno_start; i < max_regno; i++) if (reg_renumber[i] < 0 && lra_reg_info[i].nrefs != 0 - && regno_allocno_class_array[i] != NO_REGS + && (rclass = lra_get_allocno_class (i)) != NO_REGS && ! bitmap_bit_p (&non_reload_pseudos, i)) { - sorted_pseudos[n++] = i; if (! find_reload_regno_insns (i, first, last)) continue; - if (spill_hard_reg_in_range (i, regno_allocno_class_array[i], - first, last)) - return true; + if (spill_hard_reg_in_range (i, rclass, first, last)) + { + bitmap_clear (&failed_reload_pseudos); + return true; + } + bitmap_set_bit (&failed_reload_pseudos, i); } bitmap_initialize (&failed_reload_insns, ®_obstack); - for (i = 0; i < n; i++) + EXECUTE_IF_SET_IN_BITMAP (&failed_reload_pseudos, 0, u, bi) { - regno = sorted_pseudos[i]; + regno = u; bitmap_ior_into (&failed_reload_insns, &lra_reg_info[regno].insn_bitmap); - lra_setup_reg_renumber (regno, ira_class_hard_regs[regno_allocno_class_array[regno]][0], false); + lra_setup_reg_renumber + (regno, ira_class_hard_regs[lra_get_allocno_class (regno)][0], false); } EXECUTE_IF_SET_IN_BITMAP (&failed_reload_insns, 0, u, bi) { @@ -1805,5 +1810,7 @@ lra_split_hard_reg_for (void) fatal_insn ("this is the insn:", insn); } } + bitmap_clear (&failed_reload_pseudos); + bitmap_clear (&failed_reload_insns); return false; } Index: lra-constraints.c =================================================================== --- lra-constraints.c (revision 258504) +++ lra-constraints.c (working copy) @@ -5680,13 +5680,30 @@ spill_hard_reg_in_range (int regno, enum int i, hard_regno; int rclass_size; rtx_insn *insn; + unsigned int uid; + bitmap_iterator bi; + HARD_REG_SET ignore; lra_assert (from != NULL && to != NULL); + CLEAR_HARD_REG_SET (ignore); + EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) + { + lra_insn_recog_data_t id = lra_insn_recog_data[uid]; + struct lra_static_insn_data *static_id = id->insn_static_data; + struct lra_insn_reg *reg; + + for (reg = id->regs; reg != NULL; reg = reg->next) + if (reg->regno <= FIRST_PSEUDO_REGISTER) + SET_HARD_REG_BIT (ignore, reg->regno); + for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) + SET_HARD_REG_BIT (ignore, reg->regno); + } rclass_size = ira_class_hard_regs_num[rclass]; for (i = 0; i < rclass_size; i++) { hard_regno = ira_class_hard_regs[rclass][i]; - if (! TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, hard_regno)) + if (! TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, hard_regno) + || TEST_HARD_REG_BIT (ignore, hard_regno)) continue; for (insn = from; insn != NEXT_INSN (to); insn = NEXT_INSN (insn)) if (bitmap_bit_p (&lra_reg_info[hard_regno].insn_bitmap, Index: testsuite/gcc.target/i386/pr84876.c =================================================================== --- testsuite/gcc.target/i386/pr84876.c (nonexistent) +++ testsuite/gcc.target/i386/pr84876.c (working copy) @@ -0,0 +1,11 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-w" } */ + +__int128 test (__int128 a) +{ + asm ("" : "+v" (a) : : "xmm0", "xmm1", "xmm2", "xmm3", /* { dg-error "'asm' operand has impossible constraints" } */ + "xmm4", "xmm5", "xmm6", "xmm7", + "xmm8", "xmm9", "xmm10", "xmm11", + "xmm12", "xmm13", "xmm14", "xmm15"); + return a; +}