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Content preview: Hi Linus, Apologies for the _extremely_ late pull request here, but we had a 'perf' (i.e. CPU PMU) regression on the Apple M1 reported on Wednesday [1] which was introduced by bd2756811766 ("perf: Rewrite core [...] Content analysis details: (-5.4 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [139.178.84.217 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.2 DKIMWL_WL_HIGH DKIMwl.org - High trust sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org Hi Linus, Apologies for the _extremely_ late pull request here, but we had a 'perf' (i.e. CPU PMU) regression on the Apple M1 reported on Wednesday [1] which was introduced by bd2756811766 ("perf: Rewrite core context handling") during the merge window. Mark and I looked into this and noticed an additional problem caused by the same patch, where the 'CHAIN' event (used to combine two adjacent 32-bit counters into a single 64-bit counter) was not being filtered correctly. Mark posted a series on Thursday [2] which addresses both of these regressions and I queued it the same day. Unfortunately, the timing has meant that these two patches are yet to land in linux-next. We narrowly missed the 20230217 release and now we're into the weekend. The changes are small, self-contained and have been confirmed to fix the original regression, so I'd really appreciate it if you could please pull them in for 6.2 despite the caveat above. Thanks, and sorry again for the unfortunate timing. Will [1] https://lore.kernel.org/asahi/20230215-arm_pmu_m1_regression-v1-1-f5a266577c8d@jannau.net/ [2] https://lore.kernel.org/linux-arm-kernel/20230216141240.3833272-1-mark.rutland@arm.com/ --->8 The following changes since commit a428eb4b99ab80454f06ad256b25e930fe8a4954: Partially revert "perf/arm-cmn: Optimise DTC counter accesses" (2023-01-26 13:55:38 +0000) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git tags/arm64-fixes for you to fetch changes up to 853e2dac25c15f7431dfe59805de1bada34c96e9: arm64: perf: reject CHAIN events at creation time (2023-02-16 21:23:52 +0000) ---------------------------------------------------------------- arm64 regression fix for 6.2 - Fix 'perf' regression for non-standard CPU PMU hardware (i.e. Apple M1) ---------------------------------------------------------------- Mark Rutland (2): arm_pmu: fix event CPU filtering arm64: perf: reject CHAIN events at creation time arch/arm64/kernel/perf_event.c | 15 ++++++++------- drivers/perf/arm_pmu.c | 8 +------- include/linux/perf/arm_pmu.h | 1 - 3 files changed, 9 insertions(+), 15 deletions(-)