From patchwork Fri Feb 17 12:12:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Liang X-Patchwork-Id: 1744198 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4PJ9gh74KHz23j7 for ; Fri, 17 Feb 2023 23:13:04 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 6026C85959; Fri, 17 Feb 2023 13:12:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id E6E0485C1B; Fri, 17 Feb 2023 13:12:55 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00, PDS_RDNS_DYNAMIC_FP, RDNS_DYNAMIC,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9800A8574E for ; Fri, 17 Feb 2023 13:12:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 31HCCexv019563; Fri, 17 Feb 2023 20:12:40 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from ubuntu01 (10.0.12.75) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Fri, 17 Feb 2023 20:12:35 +0800 Date: Fri, 17 Feb 2023 12:12:18 +0000 From: Leo Liang To: CC: , , Subject: [PULL] u-boot-riscv/master Message-ID: MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/2.0.5 (2021-01-21) X-Originating-IP: [10.0.12.75] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 31HCCexv019563 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Hi Tom, The following changes since commit faac9dee8e0629326dc122f4624fc4897e3f38b0: Prepare v2023.04-rc2 (2023-02-13 18:39:15 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 7574b6476afc1fd76816be6567458f6ca4f44234: riscv: binman: Add help message for missing blobs (2023-02-17 19:07:48 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15225 ---------------------------------------------------------------- - binman: Add help message if opensbi is absent when building u-boot SPL - AndesTech: rename cpu and board name to 'andesv5' and 'ae350' - Clean up cache operation for Andes ae350 platform ---------------------------------------------------------------- Leo Yu-Chi Liang (3): riscv: Remove redundant Kconfig "RISCV_NDS_CACHE" riscv: Rename Andes cpu and board names riscv: ae350: Adjust the memory layout of ae350 Rick Chen (1): riscv: binman: Add help message for missing blobs Yu Chien Peter Lin (10): riscv: global_data.h: Correct the comment for PLICSW board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init() driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() riscv: ae350: dts: Update L2 cache compatible string riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL configs: ae350: Enable v5l2 cache for AE350 platforms in SPL configs: ae350: Increase maximum retry count for AE350 platforms configs: ae350: Display CPU and board info for AE350 platforms driver: cache-v5l2: Fix type casting warning on RV32 arch/riscv/Kconfig | 8 ++++---- arch/riscv/cpu/{ax25 => andesv5}/Kconfig | 11 +---------- arch/riscv/cpu/{ax25 => andesv5}/Makefile | 0 arch/riscv/cpu/andesv5/cache.c | 130 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/riscv/cpu/andesv5/cpu.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++ arch/riscv/cpu/{ax25 => andesv5}/spl.c | 0 arch/riscv/cpu/ax25/cache.c | 172 --------------------------------------------------------------------------------------------------------------------------------------------------------------------- arch/riscv/cpu/ax25/cpu.c | 75 ------------------------------------------------------------------------ arch/riscv/dts/Makefile | 2 +- arch/riscv/dts/ae350_32.dts | 2 +- arch/riscv/dts/ae350_64.dts | 2 +- arch/riscv/dts/binman.dtsi | 1 + arch/riscv/include/asm/arch-andes/csr.h | 31 ++++++++++++++++++++++++++++++ arch/riscv/include/asm/global_data.h | 2 +- board/AndesTech/{ax25-ae350 => ae350}/Kconfig | 8 ++++---- board/AndesTech/{ax25-ae350 => ae350}/MAINTAINERS | 6 +++--- board/AndesTech/{ax25-ae350 => ae350}/Makefile | 2 +- board/AndesTech/{ax25-ae350/ax25-ae350.c => ae350/ae350.c} | 17 +++++++++-------- configs/ae350_rv32_defconfig | 5 ++++- configs/ae350_rv32_spl_defconfig | 13 +++++++++---- configs/ae350_rv32_spl_xip_defconfig | 13 +++++++++---- configs/ae350_rv32_xip_defconfig | 5 ++++- configs/ae350_rv64_defconfig | 5 ++++- configs/ae350_rv64_spl_defconfig | 13 +++++++++---- configs/ae350_rv64_spl_xip_defconfig | 13 +++++++++---- configs/ae350_rv64_xip_defconfig | 5 ++++- doc/board/AndesTech/{ax25-ae350.rst => ae350.rst} | 16 ++++++++-------- doc/board/AndesTech/index.rst | 2 +- drivers/cache/Kconfig | 1 - drivers/cache/cache-v5l2.c | 36 +++++++++++++++++++++++++---------- include/configs/{ax25-ae350.h => ae350.h} | 0 tools/binman/missing-blob-help | 6 ++++++ 32 files changed, 331 insertions(+), 321 deletions(-) rename arch/riscv/cpu/{ax25 => andesv5}/Kconfig (66%) rename arch/riscv/cpu/{ax25 => andesv5}/Makefile (100%) create mode 100644 arch/riscv/cpu/andesv5/cache.c create mode 100644 arch/riscv/cpu/andesv5/cpu.c rename arch/riscv/cpu/{ax25 => andesv5}/spl.c (100%) delete mode 100644 arch/riscv/cpu/ax25/cache.c delete mode 100644 arch/riscv/cpu/ax25/cpu.c create mode 100644 arch/riscv/include/asm/arch-andes/csr.h rename board/AndesTech/{ax25-ae350 => ae350}/Kconfig (88%) rename board/AndesTech/{ax25-ae350 => ae350}/MAINTAINERS (80%) rename board/AndesTech/{ax25-ae350 => ae350}/Makefile (87%) rename board/AndesTech/{ax25-ae350/ax25-ae350.c => ae350/ae350.c} (95%) rename doc/board/AndesTech/{ax25-ae350.rst => ae350.rst} (98%) rename include/configs/{ax25-ae350.h => ae350.h} (100%) Best regards, Leo