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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id m187-20020a633fc4000000b004faf33e2758sm337300pga.40.2023.02.12.03.34.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Feb 2023 03:34:05 -0800 (PST) To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, juzhe.zhong@rivai.ai Cc: Kito Cheng Subject: [PATCH] RISC-V: Handle vlenb correctly in unwinding Date: Sun, 12 Feb 2023 19:33:59 +0800 Message-Id: <20230212113359.18239-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Kito Cheng via Gcc-patches From: Kito Cheng Reply-To: Kito Cheng Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" gcc/ChangeLog: * config/riscv/riscv.h (RISCV_DWARF_VLENB): New. (DWARF_FRAME_REGISTERS): New. (DWARF_REG_TO_UNWIND_COLUMN): New. libgcc/ChangeLog: * config.host (riscv*-*-*): Add config/riscv/value-unwind.h. * config/riscv/value-unwind.h: New. --- gcc/config/riscv/riscv.h | 7 ++++++ libgcc/config.host | 3 +++ libgcc/config/riscv/value-unwind.h | 39 ++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+) create mode 100644 libgcc/config/riscv/value-unwind.h diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 120faf17c06..5bc7f2f467d 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -1088,4 +1088,11 @@ extern void riscv_remove_unneeded_save_restore_calls (void); #define REGMODE_NATURAL_SIZE(MODE) riscv_regmode_natural_size (MODE) +#define RISCV_DWARF_VLENB (4096 + 0xc22) + +#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 1 /* VLENB */) + +#define DWARF_REG_TO_UNWIND_COLUMN(REGNO) \ + ((REGNO == RISCV_DWARF_VLENB) ? (FIRST_PSEUDO_REGISTER + 1) : REGNO) + #endif /* ! GCC_RISCV_H */ diff --git a/libgcc/config.host b/libgcc/config.host index 70d47e08e40..b9975de9023 100644 --- a/libgcc/config.host +++ b/libgcc/config.host @@ -1559,6 +1559,9 @@ aarch64*-*-*) # ILP32 needs an extra header for unwinding tm_file="${tm_file} aarch64/value-unwind.h" ;; +riscv*-*-*) + tm_file="${tm_file} riscv/value-unwind.h" + ;; esac # Setup to build a shared libgcc for VxWorks when that was requested, diff --git a/libgcc/config/riscv/value-unwind.h b/libgcc/config/riscv/value-unwind.h new file mode 100644 index 00000000000..d7efdc14e6f --- /dev/null +++ b/libgcc/config/riscv/value-unwind.h @@ -0,0 +1,39 @@ +/* Store register values as _Unwind_Word type in DWARF2 EH unwind context. + Copyright (C) 2023 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +/* Return the value of the VLENB register. This should only be + called if we know this is an vector extension enabled RISC-V host. */ +static inline long +riscv_vlenb (void) +{ + register long vlenb asm ("a0"); + /* 0xc2202573 == csrr a0, 0xc22 */ + asm (".insn 0xc2202573" : "=r"(vlenb)); + return vlenb; +} + +/* Lazily provide a value for VLENB, so that we don't try to execute RVV + instructions unless we know they're needed. */ +#define DWARF_LAZY_REGISTER_VALUE(REGNO, VALUE) \ + ((REGNO) == RISCV_DWARF_VLENB && ((*VALUE) = riscv_vlenb (), 1))