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Tue, 7 Feb 2023 15:08:38 +0000 (GMT) Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5024320040; Tue, 7 Feb 2023 15:08:38 +0000 (GMT) Received: from borneo.home (unknown [9.171.73.180]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 7 Feb 2023 15:08:38 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org, arbab@linux.ibm.com Date: Tue, 7 Feb 2023 16:08:36 +0100 Message-Id: <20230207150837.99476-1-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: ZeujilpAVmMKtqhGH7vfOguiDY4zlokU X-Proofpoint-GUID: 5UAoSlUsNyC55JjKD9fCspA0N2syKHr5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-07_07,2023-02-06_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 impostorscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 clxscore=1015 malwarescore=0 phishscore=0 priorityscore=1501 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302070135 Subject: [Skiboot] [PATCH 1/2] hw/phb4: Use symbols when accessing PEC registers X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: clombard@linux.ibm.com, 867314078@qq.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This patch improves readability just a tiny bit by using symbols, most of them already existing, instead of values when accessing the PEC registers. No functional changes. Signed-off-by: Frederic Barrat --- hw/phb4.c | 30 ++++++++++++++++++------------ include/phb4-regs.h | 1 + 2 files changed, 19 insertions(+), 12 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index f329e130..e0156469 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -1950,11 +1950,11 @@ static void phb4_read_phb_status(struct phb4 *p, /* PEC NFIR, same as P8/PHB3 */ - xscom_read(p->chip_id, p->pe_stk_xscom + 0x0, &__64); + xscom_read(p->chip_id, p->pe_stk_xscom + XPEC_NEST_STK_PCI_NFIR, &__64); stat->nFir = cpu_to_be64(__64); - xscom_read(p->chip_id, p->pe_stk_xscom + 0x3, &__64); + xscom_read(p->chip_id, p->pe_stk_xscom + XPEC_NEST_STK_PCI_NFIR_MSK, &__64); stat->nFirMask = cpu_to_be64(__64); - xscom_read(p->chip_id, p->pe_stk_xscom + 0x8, &__64); + xscom_read(p->chip_id, p->pe_stk_xscom + XPEC_NEST_STK_PCI_NFIR_WOF, &__64); stat->nFirWOF = cpu_to_be64(__64); /* PHB4 inbound and outbound error Regs */ @@ -3508,7 +3508,8 @@ static int64_t phb4_creset(struct pci_slot *slot) phb4_prepare_link_change(slot, false); /* Clear error inject register, preventing recursive errors */ - xscom_write(p->chip_id, p->pe_xscom + 0x2, 0x0); + xscom_write(p->chip_id, p->pe_xscom + XPEC_NEST_PBCQ_ERR_INJECT, + 0x0); /* Prevent HMI when PHB gets fenced as we are disabling CAPP */ if (p->flags & PHB4_CAPP_DISABLE && @@ -3522,7 +3523,8 @@ static int64_t phb4_creset(struct pci_slot *slot) /* Force fence on the PHB to work around a non-existent PE */ if (!phb4_fenced(p)) - xscom_write(p->chip_id, p->pe_stk_xscom + 0x2, + xscom_write(p->chip_id, + p->pe_stk_xscom + XPEC_NEST_STK_PCI_NFIR_SET, 0x0000002000000000UL); /* @@ -3543,8 +3545,10 @@ static int64_t phb4_creset(struct pci_slot *slot) 0x8000000000000000UL); /* Read errors in PFIR and NFIR */ - xscom_read(p->chip_id, p->pci_stk_xscom + 0x0, &p->pfir_cache); - xscom_read(p->chip_id, p->pe_stk_xscom + 0x0, &p->nfir_cache); + xscom_read(p->chip_id, p->pci_stk_xscom + XPEC_PCI_STK_PCI_FIR, + &p->pfir_cache); + xscom_read(p->chip_id, p->pe_stk_xscom + XPEC_NEST_STK_PCI_NFIR, + &p->nfir_cache); pci_slot_set_state(slot, PHB4_SLOT_CRESET_WAIT_CQ); slot->retries = 500; @@ -3552,7 +3556,9 @@ static int64_t phb4_creset(struct pci_slot *slot) case PHB4_SLOT_CRESET_WAIT_CQ: // Wait until operations are complete - xscom_read(p->chip_id, p->pe_stk_xscom + 0xc, &pbcq_status); + xscom_read(p->chip_id, + p->pe_stk_xscom + XPEC_NEST_STK_PBCQ_STAT, + &pbcq_status); if (!(pbcq_status & 0xC000000000000000UL)) { PHBDBG(p, "CRESET: No pending transactions\n"); @@ -3565,10 +3571,10 @@ static int64_t phb4_creset(struct pci_slot *slot) disable_capi_mode(p); /* Clear errors in PFIR and NFIR */ - xscom_write(p->chip_id, p->pci_stk_xscom + 0x1, - ~p->pfir_cache); - xscom_write(p->chip_id, p->pe_stk_xscom + 0x1, - ~p->nfir_cache); + xscom_write(p->chip_id, p->pci_stk_xscom + + XPEC_PCI_STK_PCI_FIR_CLR, ~p->pfir_cache); + xscom_write(p->chip_id, p->pe_stk_xscom + + XPEC_NEST_STK_PCI_NFIR_CLR, ~p->nfir_cache); /* Re-read errors in PFIR and NFIR and reset any new * error reported. diff --git a/include/phb4-regs.h b/include/phb4-regs.h index b4a94c05..a27efbb2 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -325,6 +325,7 @@ #define XPEC_NEST_PBCQ_HW_CONFIG_CH_STR PPC_BIT(33) #define XPEC_NEST_PBCQ_HW_CONFIG_DIS_NODAL PPC_BIT(50) #define XPEC_NEST_PBCQ_HW_CONFIG_DIS_RNNN PPC_BIT(52) +#define XPEC_NEST_PBCQ_ERR_INJECT 0x2 #define XPEC_NEST_CAPP_CNTL 0x7 #define XPEC_NEST_READ_STACK_OVERRIDE 0x8 From patchwork Tue Feb 7 15:08:37 2023 Content-Type: text/plain; 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Tue, 7 Feb 2023 15:08:39 GMT Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 28AE52004E; Tue, 7 Feb 2023 15:08:39 +0000 (GMT) Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C42522004F; Tue, 7 Feb 2023 15:08:38 +0000 (GMT) Received: from borneo.home (unknown [9.171.73.180]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 7 Feb 2023 15:08:38 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org, arbab@linux.ibm.com Date: Tue, 7 Feb 2023 16:08:37 +0100 Message-Id: <20230207150837.99476-2-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230207150837.99476-1-fbarrat@linux.ibm.com> References: <20230207150837.99476-1-fbarrat@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: woc9UiXK2-Ovy6pAWydNQ6B9sugeMLmf X-Proofpoint-GUID: wIoGy_QNlvnbcwmmN9WRQkD_KzNjKRQo X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-07_07,2023-02-06_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 impostorscore=0 phishscore=0 mlxscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 spamscore=0 mlxlogscore=873 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302070135 Subject: [Skiboot] [PATCH 2/2] hw/phb4: Clear the PEC FIRs when taking the ETU out of reset X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: clombard@linux.ibm.com, 867314078@qq.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The documented PEC recovery procedure is to clear the PEC FIR registers when the ETU/PHB is in reset. However, any xscom access targeting a PHB register while it is in reset will raise a new error (PFIR bit 3), so it is possible to get out of reset and still have a FIR register showing errors. It has been observed that the OCC, through its 24x7 service, can do such a xscom access at boot time if we end up in the CRESET path. So the current behavior of logging an error is not desirable. The recommendation from the logic designer is to keep the existing mechanism to clear the FIR registers and add an extra step to clear any new errors immediately after taking the ETU out of reset. That's what this patch is doing. Fixes: https://github.com/open-power/skiboot/issues/273 Signed-off-by: Frederic Barrat --- hw/phb4.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index e0156469..b1fa08fe 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3576,8 +3576,19 @@ static int64_t phb4_creset(struct pci_slot *slot) xscom_write(p->chip_id, p->pe_stk_xscom + XPEC_NEST_STK_PCI_NFIR_CLR, ~p->nfir_cache); - /* Re-read errors in PFIR and NFIR and reset any new - * error reported. + /* Clear PHB from reset */ + xscom_write(p->chip_id, + p->pci_stk_xscom + XPEC_PCI_STK_ETU_RESET, 0x0); + p->flags &= ~PHB4_ETU_IN_RESET; + + /* + * Re-read errors in PFIR and NFIR and reset + * any new error reported while the ETU was in + * reset. + * A xscom access when the ETU is in reset + * will set PFIR bit 3 and the OCC is known to + * access PHB performance counters, so such an + * error is not uncommon. */ xscom_read(p->chip_id, p->pci_stk_xscom + XPEC_PCI_STK_PCI_FIR, &p->pfir_cache); @@ -3585,21 +3596,14 @@ static int64_t phb4_creset(struct pci_slot *slot) XPEC_NEST_STK_PCI_NFIR, &p->nfir_cache); if (p->pfir_cache || p->nfir_cache) { - PHBERR(p, "CRESET: PHB still fenced !!\n"); - phb4_dump_pec_err_regs(p); - - /* Reset the PHB errors */ xscom_write(p->chip_id, p->pci_stk_xscom + - XPEC_PCI_STK_PCI_FIR, 0); + XPEC_PCI_STK_PCI_FIR_CLR, + ~p->pfir_cache); xscom_write(p->chip_id, p->pe_stk_xscom + - XPEC_NEST_STK_PCI_NFIR, 0); + XPEC_NEST_STK_PCI_NFIR_CLR, + ~p->nfir_cache); } - /* Clear PHB from reset */ - xscom_write(p->chip_id, - p->pci_stk_xscom + XPEC_PCI_STK_ETU_RESET, 0x0); - p->flags &= ~PHB4_ETU_IN_RESET; - pci_slot_set_state(slot, PHB4_SLOT_CRESET_REINIT); /* After lifting PHB reset, wait while logic settles */ return pci_slot_set_sm_timeout(slot, msecs_to_tb(10));