From patchwork Fri Feb 3 07:04:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 1736716 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4P7RWV0tvDz23hn for ; Fri, 3 Feb 2023 18:05:42 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0609B385828D for ; Fri, 3 Feb 2023 07:05:40 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by sourceware.org (Postfix) with ESMTPS id 6BCFC3858C5E for ; Fri, 3 Feb 2023 07:04:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6BCFC3858C5E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp68t1675407891tidie6zj Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 03 Feb 2023 15:04:50 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: bhet8yMU7vlGZm4KTIqxgZCOegmdjYey0gq+XeJV1ZrlAp6XzRZF+W9PaFE7I wKg4jashMvNEGjf1pPWP5hET+xR+EYy1sLLA312R6+7EnpHgeF6RFYQZ0BT5Jznuj0qhE57 6ECXaJRX261Zj5o54SJ+WOjcVU7VqmBTolLmRhzP2epykVKZI5cr4rOGq/LdGruzi7V0O88 /IaWv3uj+Pl3U1R8lnvrLZIsgCxTVpJmE4F7mJnEDLgcpdw6q/u4OGOH8ksl6TAht9SE3sl o+SmIIw3qak7nWM21UgZc+RjO5JZKM2XRIPeWzwI0Rx/0UyajAq4F3Bn4qx4IMzqCaLW9H2 BsvANBSVOMEMbOEc84dBp4UrPinKX1K47Dx0VibtjuXunMbFkDDmWFn0gWTPxErjoR29MZX X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vxor.vx C API tests Date: Fri, 3 Feb 2023 15:04:49 +0800 Message-Id: <20230203070449.158742-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vxor_vx_m_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_m_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_m_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_m_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_m_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_m_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-3.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-3.c: New test. --- .../riscv/rvv/base/vxor_vx_m_rv32-1.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_m_rv32-2.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_m_rv32-3.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_m_rv64-1.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_m_rv64-2.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_m_rv64-3.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_mu_rv32-1.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_mu_rv32-2.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_mu_rv32-3.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_mu_rv64-1.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_mu_rv64-2.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_mu_rv64-3.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_rv32-1.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_rv32-2.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_rv32-3.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_rv64-1.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_rv64-2.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_rv64-3.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_tu_rv32-1.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_tu_rv32-2.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_tu_rv32-3.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_tu_rv64-1.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_tu_rv64-2.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_tu_rv64-3.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_tum_rv32-1.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_tum_rv32-2.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_tum_rv32-3.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_tum_rv64-1.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_tum_rv64-2.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_tum_rv64-3.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_tumu_rv32-1.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_tumu_rv32-2.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_tumu_rv32-3.c | 289 +++++++++++++++++ .../riscv/rvv/base/vxor_vx_tumu_rv64-1.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_tumu_rv64-2.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vx_tumu_rv64-3.c | 292 ++++++++++++++++++ 36 files changed, 10458 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv32-1.c new file mode 100644 index 00000000000..0c3e99b2455 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv32-1.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_m(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_m(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_m(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_m(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_m(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_m(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_m(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_m(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_m(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_m(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_m(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_m(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_m(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_m(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_m(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_m(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_m(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_m(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_m(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_m(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_m(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_m(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_m(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_m(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_m(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_m(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_m(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_m(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_m(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_m(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_m(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_m(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_m(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_m(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_m(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_m(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_m(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_m(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_m(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_m(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_m(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_m(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_m(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv32-2.c new file mode 100644 index 00000000000..a6d6f8867b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv32-2.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_m(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_m(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_m(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_m(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_m(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_m(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_m(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_m(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_m(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_m(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_m(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_m(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_m(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_m(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_m(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_m(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_m(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_m(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_m(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_m(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_m(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_m(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_m(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_m(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_m(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_m(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_m(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_m(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_m(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_m(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_m(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_m(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_m(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_m(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_m(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_m(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_m(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_m(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_m(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_m(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_m(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_m(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_m(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv32-3.c new file mode 100644 index 00000000000..fec074089ec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv32-3.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_m(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_m(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_m(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_m(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_m(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_m(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_m(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_m(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_m(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_m(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_m(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_m(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_m(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_m(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_m(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_m(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_m(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_m(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_m(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_m(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_m(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_m(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_m(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_m(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_m(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_m(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_m(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_m(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_m(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_m(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_m(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_m(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_m(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_m(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_m(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_m(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_m(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_m(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_m(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_m(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_m(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_m(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_m(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv64-1.c new file mode 100644 index 00000000000..f4522dae5fa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv64-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_m(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_m(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_m(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_m(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_m(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_m(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_m(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_m(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_m(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_m(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_m(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_m(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_m(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_m(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_m(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_m(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_m(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_m(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_m(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_m(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_m(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_m(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_m(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_m(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_m(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_m(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_m(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_m(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_m(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_m(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_m(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_m(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_m(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_m(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_m(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_m(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_m(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_m(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_m(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_m(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_m(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_m(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_m(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv64-2.c new file mode 100644 index 00000000000..c1da7960bed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv64-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_m(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_m(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_m(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_m(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_m(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_m(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_m(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_m(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_m(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_m(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_m(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_m(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_m(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_m(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_m(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_m(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_m(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_m(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_m(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_m(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_m(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_m(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_m(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_m(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_m(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_m(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_m(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_m(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_m(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_m(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_m(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_m(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_m(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_m(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_m(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_m(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_m(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_m(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_m(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_m(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_m(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_m(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_m(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv64-3.c new file mode 100644 index 00000000000..65fc8869c4b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv64-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_m(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_m(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_m(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_m(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_m(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_m(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_m(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_m(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_m(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_m(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_m(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_m(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_m(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_m(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_m(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_m(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_m(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_m(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_m(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_m(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_m(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_m(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_m(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_m(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_m(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_m(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_m(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_m(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_m(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_m(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_m(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_m(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_m(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_m(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_m(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_m(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_m(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_m(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_m(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_m(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_m(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_m(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_m(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-1.c new file mode 100644 index 00000000000..f02e7182de4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-1.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-2.c new file mode 100644 index 00000000000..d8a539bce0c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-2.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-3.c new file mode 100644 index 00000000000..a5e0be83a4f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-3.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-1.c new file mode 100644 index 00000000000..02a2f628f8f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-2.c new file mode 100644 index 00000000000..64004cb780f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-3.c new file mode 100644 index 00000000000..e876537ea40 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv32-1.c new file mode 100644 index 00000000000..dcab712de09 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv32-1.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2(op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1(op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2(op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4(op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2(op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1(op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2(op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4(op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2(op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1(op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2(op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4(op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8(op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1(op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2(op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4(op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv32-2.c new file mode 100644 index 00000000000..8474aabac95 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv32-2.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8(op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4(op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2(op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1(op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2(op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4(op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8(op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4(op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2(op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1(op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2(op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4(op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8(op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2(op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1(op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2(op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4(op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8(op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1(op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2(op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4(op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2(op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1(op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2(op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4(op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2(op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1(op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2(op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4(op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2(op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1(op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2(op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4(op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8(op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1(op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2(op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4(op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv32-3.c new file mode 100644 index 00000000000..211bbb8a01a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv32-3.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8(op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4(op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2(op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1(op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2(op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4(op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8(op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4(op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2(op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1(op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2(op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4(op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8(op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2(op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1(op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2(op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4(op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8(op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1(op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2(op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4(op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2(op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1(op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2(op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4(op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2(op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1(op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2(op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4(op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2(op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1(op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2(op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4(op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8(op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1(op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2(op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4(op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv64-1.c new file mode 100644 index 00000000000..3bb3ae6e1a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv64-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2(op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1(op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2(op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4(op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2(op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1(op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2(op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4(op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2(op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1(op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2(op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4(op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8(op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1(op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2(op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4(op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv64-2.c new file mode 100644 index 00000000000..7311d8c82bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv64-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8(op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4(op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2(op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1(op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2(op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4(op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8(op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4(op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2(op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1(op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2(op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4(op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8(op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2(op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1(op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2(op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4(op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8(op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1(op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2(op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4(op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2(op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1(op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2(op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4(op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2(op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1(op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2(op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4(op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2(op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1(op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2(op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4(op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8(op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1(op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2(op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4(op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv64-3.c new file mode 100644 index 00000000000..489a776954d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv64-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8(op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4(op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2(op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1(op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2(op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4(op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8(op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4(op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2(op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1(op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2(op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4(op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8(op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2(op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1(op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2(op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4(op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8(op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1(op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2(op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4(op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2(op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1(op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2(op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4(op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2(op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1(op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2(op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4(op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2(op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1(op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2(op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4(op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8(op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1(op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2(op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4(op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-1.c new file mode 100644 index 00000000000..0be3812793a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-1.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-2.c new file mode 100644 index 00000000000..31d65ca0606 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-2.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-3.c new file mode 100644 index 00000000000..9353df0fa0e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-3.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-1.c new file mode 100644 index 00000000000..496d0564655 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-2.c new file mode 100644 index 00000000000..995310b9929 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-3.c new file mode 100644 index 00000000000..94864f25477 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-1.c new file mode 100644 index 00000000000..9675f3d3591 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-1.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-2.c new file mode 100644 index 00000000000..d6f420b9b2e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-2.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-3.c new file mode 100644 index 00000000000..3dacf4a7536 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-3.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-1.c new file mode 100644 index 00000000000..5887c8ccedf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-2.c new file mode 100644 index 00000000000..4404f723975 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-3.c new file mode 100644 index 00000000000..e2ef963b77d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-1.c new file mode 100644 index 00000000000..1dcf6d6ba45 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-1.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-2.c new file mode 100644 index 00000000000..d1025c8abb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-2.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-3.c new file mode 100644 index 00000000000..13b9f0f9402 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-3.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-1.c new file mode 100644 index 00000000000..99c0a87dc5b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-2.c new file mode 100644 index 00000000000..12a28e1f8d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-3.c new file mode 100644 index 00000000000..9e0a81971e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf8_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf4_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8mf2_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m1_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m2_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m4_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vxor_vx_i8m8_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf4_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16mf2_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m1_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m2_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m4_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vxor_vx_i16m8_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32mf2_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m1_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m2_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m4_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vxor_vx_i32m8_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m1_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m2_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m4_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vxor_vx_i64m8_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf8_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf4_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m1_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m2_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m4_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vxor_vx_u8m8_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf4_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m1_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m4_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vxor_vx_u16m8_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m1_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m4_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vxor_vx_u32m8_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m1_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m2_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m4_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vxor_vx_u64m8_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */