From patchwork Tue Jan 31 22:15:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 1735114 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4P5zrl1mtWz23hd for ; Wed, 1 Feb 2023 09:15:35 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4336A3858434 for ; Tue, 31 Jan 2023 22:15:33 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by sourceware.org (Postfix) with ESMTPS id 2E4963858D33 for ; Tue, 31 Jan 2023 22:15:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2E4963858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp81t1675203315tl5mh0jv Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 01 Feb 2023 06:15:14 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: LG+NUo/f6sEmkOfqpaxT2BNoisa+8WWXPbT/rhIV0iiWJDWY8C149RxEp/5Ae yHhFpD0v9fCNe2N/OgvgyYg/6JQ/0jhxzAUycRlrwZgexPRm2+YR91GCaHJVO92lzmtjMao zi1EfWWrfnvF1UpopS9LHCkgEkItfbXoN4HvaU9utN/rkrwnZmbilkXtdFMs0NFVJIwvU8/ OU7ypDVs+w1tXQzR+TOJUbM84oCBVrAO58j/VwRgI6hAuWnucaNo34vuRUKmT98Es4XwHGT dX9cf1V0gZG9gIQ9io/hYiTylW4eUO28lC+KoXlujomvBGeAdeL7DcKIHVv0y8BojZFztIq Aqe3KX8rWHkdXd/fJb2bLbdyIhgk8qM2/b8TRsQGNFlN/OcsT0fmR0V7N9J+A== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add shift constraint tests Date: Wed, 1 Feb 2023 06:15:13 +0800 Message-Id: <20230131221513.22652-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: New test. --- .../riscv/rvv/base/shift_vx_constraint-1.c | 133 ++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c new file mode 100644 index 00000000000..ae3883c5af9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c @@ -0,0 +1,133 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\tzero,4,e32,m1,tu,ma +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,31 +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,31 +** vse32\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vsll_vx_i32m1 (v2, 31, 4); + vint32m1_t v4 = __riscv_vsll_vx_i32m1_tu (v3, v2, 31, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** ... +** vsetivli\tzero,4,e32,m1,ta,ma +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** vse32.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vsll_vx_i32m1 (v2, 32, 4); + vint32m1_t v4 = __riscv_vsll_vx_i32m1_m (mask, v3, 32, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,tu,mu +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*17 +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*17,\s*v0.t +** vse32.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vsll_vx_i32m1 (v2, 17, 4); + vint32m1_t v4 = __riscv_vsll_vx_i32m1_tumu (mask, v3, v2, 17, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f4: +** vsetivli\tzero,4,e8,mf8,tu,ma +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vse8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f4 (void * in, void *out, size_t x) +{ + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in, 4); + vint8mf8_t v3 = __riscv_vsll_vx_i8mf8 (v2, x, 4); + vint8mf8_t v4 = __riscv_vsll_vx_i8mf8_tu (v3, v2, x, 4); + __riscv_vse8_v_i8mf8 (out, v4, 4); +} + +/* +** f5: +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e8,mf8,ta,ma +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*5 +** vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*5,\s*v0.t +** vse8.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f5 (void * in, void *out) +{ + vbool64_t mask = *(vbool64_t*)in; + asm volatile ("":::"memory"); + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_m (mask, in, 4); + vint8mf8_t v3 = __riscv_vsll_vx_i8mf8 (v2, 5, 4); + vint8mf8_t v4 = __riscv_vsll_vx_i8mf8_m (mask, v3, 5, 4); + __riscv_vse8_v_i8mf8 (out, v4, 4); +} + +/* +** f6: +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e8,mf8,tu,mu +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t +** vse8.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f6 (void * in, void *out, size_t x) +{ + vbool64_t mask = *(vbool64_t*)in; + asm volatile ("":::"memory"); + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in, 4); + vint8mf8_t v3 = __riscv_vsll_vx_i8mf8 (v2, x, 4); + vint8mf8_t v4 = __riscv_vsll_vx_i8mf8_tumu (mask, v3, v2, x, 4); + __riscv_vse8_v_i8mf8 (out, v4, 4); +}