From patchwork Tue Jan 31 12:12:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 1734810 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4P5kT52xPRz23gY for ; Tue, 31 Jan 2023 23:12:40 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4CB453858024 for ; Tue, 31 Jan 2023 12:12:38 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by sourceware.org (Postfix) with ESMTPS id 028BE3858D28 for ; Tue, 31 Jan 2023 12:12:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 028BE3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp89t1675167128t57m9s26 Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 31 Jan 2023 20:12:07 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: ddv/5a5hb5JnCckqEaxSrukM2j6prP1VpTZNmjFyu6QU/s3UqJXxl1kthn5oH n+mrwhWMsvzQ4GUlwMlYY56WHKZsK+4Vgh+KBZ+1SED72oCMx2H58ZoEHRAyP7tHW13IT0m QiFv8vp+ZL+xw7AutXfPzYbxhyhQjZ49F0Vv4/eelbuW6vhMLrcKTlSY4e3ZTOcUBWjcFrU hqKWT3yDELnPQMKanVCx2+D0H7Nfpt+mcZhI56U93QXxzBdVWLcARMNeGhLxmfvmmKGMzr8 R18J6nMiyz5nEZ/VEOqkC86dr/aCKSdWfGXhzxvPWIIZUbU6IHhzsMDMLjokOJjPB6JLQIr tXbgZQbmWhtQTP6ovfpr5xBNK+mhuUJ5p8y2z5KPrzAT8zBOLLkoClYwmL+q89M+p2feFdT X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vxor.vv C API tests Date: Tue, 31 Jan 2023 20:12:06 +0800 Message-Id: <20230131121206.301304-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vxor_vv-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vv-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vv-3.c: New test. * gcc.target/riscv/rvv/base/vxor_vv_m-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vv_m-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vv_m-3.c: New test. * gcc.target/riscv/rvv/base/vxor_vv_mu-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vv_mu-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vv_mu-3.c: New test. * gcc.target/riscv/rvv/base/vxor_vv_tu-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vv_tu-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vv_tu-3.c: New test. * gcc.target/riscv/rvv/base/vxor_vv_tum-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vv_tum-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vv_tum-3.c: New test. * gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vxor_vv-1.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vxor_vv-2.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vxor_vv-3.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vxor_vv_m-1.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vxor_vv_m-2.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vxor_vv_m-3.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vxor_vv_mu-1.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vxor_vv_mu-2.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vxor_vv_mu-3.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vxor_vv_tu-1.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vxor_vv_tu-2.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vxor_vv_tu-3.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vxor_vv_tum-1.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vxor_vv_tum-2.c | 292 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vxor_vv_tum-3.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vv_tumu-1.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vv_tumu-2.c | 292 ++++++++++++++++++ .../riscv/rvv/base/vxor_vv_tumu-3.c | 292 ++++++++++++++++++ 18 files changed, 5256 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-1.c new file mode 100644 index 00000000000..3f6ff8fa4a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2(op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1(op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2(op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4(op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8(vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2(op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1(op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2(op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4(op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8(vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2(op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1(op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2(op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4(op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8(vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8(op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1(vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1(op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2(vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2(op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4(vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4(op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8(vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8(vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8(vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8(vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1(vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2(vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4(vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8(vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-2.c new file mode 100644 index 00000000000..9b60835fc07 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8(op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4(op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2(op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1(op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2(op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4(op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8(vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8(op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4(op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2(op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1(op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2(op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4(op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8(vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8(op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2(op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1(op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2(op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4(op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8(vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8(op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1(vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1(op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2(vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2(op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4(vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4(op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8(vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2(op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1(op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2(op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4(op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8(vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2(op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1(op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2(op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4(op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8(vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2(op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1(op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2(op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4(op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8(vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8(op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1(vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1(op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2(vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2(op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4(vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4(op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8(vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-3.c new file mode 100644 index 00000000000..09a877dbca3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8(op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4(op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2(op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1(op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2(op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4(op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8(vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8(op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4(op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2(op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1(op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2(op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4(op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8(vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8(op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2(op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1(op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2(op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4(op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8(vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8(op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1(vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1(op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2(vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2(op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4(vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4(op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8(vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2(op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1(op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2(op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4(op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8(vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2(op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1(op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2(op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4(op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8(vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2(op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1(op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2(op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4(op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8(vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8(op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1(vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1(op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2(vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2(op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4(vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4(op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8(vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-1.c new file mode 100644 index 00000000000..fbe06e204b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8_m(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4_m(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2_m(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1_m(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2_m(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4_m(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8_m(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8_m(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4_m(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2_m(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1_m(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2_m(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4_m(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8_m(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8_m(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2_m(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1_m(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2_m(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4_m(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8_m(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8_m(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1_m(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1_m(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2_m(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2_m(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4_m(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4_m(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8_m(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8_m(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4_m(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2_m(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1_m(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2_m(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4_m(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8_m(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4_m(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2_m(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1_m(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2_m(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4_m(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8_m(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2_m(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1_m(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2_m(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4_m(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8_m(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1_m(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2_m(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4_m(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-2.c new file mode 100644 index 00000000000..3797b5d9b0e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8_m(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4_m(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2_m(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1_m(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2_m(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4_m(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8_m(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8_m(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4_m(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2_m(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1_m(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2_m(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4_m(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8_m(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8_m(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2_m(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1_m(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2_m(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4_m(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8_m(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8_m(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1_m(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1_m(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2_m(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2_m(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4_m(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4_m(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8_m(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8_m(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4_m(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2_m(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1_m(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2_m(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4_m(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8_m(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4_m(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2_m(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1_m(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2_m(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4_m(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8_m(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2_m(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1_m(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2_m(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4_m(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8_m(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1_m(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2_m(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4_m(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-3.c new file mode 100644 index 00000000000..4459be0b7cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8_m(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4_m(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2_m(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1_m(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2_m(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4_m(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8_m(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8_m(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4_m(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2_m(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1_m(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2_m(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4_m(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8_m(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8_m(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2_m(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1_m(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2_m(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4_m(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8_m(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8_m(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1_m(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1_m(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2_m(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2_m(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4_m(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4_m(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8_m(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8_m(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4_m(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2_m(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1_m(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2_m(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4_m(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8_m(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4_m(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2_m(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1_m(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2_m(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4_m(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8_m(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2_m(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1_m(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2_m(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4_m(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8_m(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1_m(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2_m(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4_m(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-1.c new file mode 100644 index 00000000000..93591b37dd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-2.c new file mode 100644 index 00000000000..f9608597cde --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-3.c new file mode 100644 index 00000000000..96cde136530 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-1.c new file mode 100644 index 00000000000..195d586c9ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-2.c new file mode 100644 index 00000000000..c5ee28d1529 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-3.c new file mode 100644 index 00000000000..cf337a642d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-1.c new file mode 100644 index 00000000000..08c25d5a408 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-2.c new file mode 100644 index 00000000000..19151015cf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-3.c new file mode 100644 index 00000000000..f38eae4f4e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c new file mode 100644 index 00000000000..bb95ccd9063 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c new file mode 100644 index 00000000000..819f742ee86 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c new file mode 100644 index 00000000000..7c463fa10fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_vv_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf8_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_vv_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf4_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_vv_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8mf2_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_vv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m1_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_vv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m2_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_vv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m4_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_vv_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i8m8_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf4_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16mf2_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_vv_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m1_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_vv_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m2_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_vv_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m4_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_vv_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i16m8_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32mf2_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_vv_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m1_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_vv_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m2_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_vv_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m4_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_vv_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i32m8_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_vv_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m1_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_vv_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m2_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_vv_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m4_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_vv_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_i64m8_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf8_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf4_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m1_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m2_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m4_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u8m8_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf4_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m1_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m4_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u16m8_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m1_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m4_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u32m8_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m1_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m2_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m4_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_vv_u64m8_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */