From patchwork Tue Jan 3 01:39:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 1720863 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NmFmh6Qbvz23dq for ; Tue, 3 Jan 2023 12:40:34 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 78A643858423 for ; Tue, 3 Jan 2023 01:40:24 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by sourceware.org (Postfix) with ESMTPS id B8B793858D37 for ; Tue, 3 Jan 2023 01:40:08 +0000 (GMT) X-QQ-mid: bizesmtp68t1672709999tedcdgdw Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 03 Jan 2023 09:39:58 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: oH0qrucfWSysqB6nkkSV9YPZbD+SLN6hJzmdpM3YZ6sUiBOO//Zbwz+FlMWRX iirAZO+G77imHzHmn52zenOwGNRilrNNrsZNZ8EDsipAWMoLn6fZKhZdVGoiAFN+CpKZ1Wl leLL7NDMfDBf4jLHOdzu0ivwuN+XjXEKMY2XsFpBT00sgJCS40twfFyDgcQGN/NQQml9CCF 3fdbB50hChQJCAQ8TEPqr9DifK60OQLis97O7hB9CQg/ye7VRk7ED5kYaj+dERWazYkoTV/ 4illfOs9ZmAB2B/DBQol8J4vdoK294UXq5czpkq3zxon/zbv+4MT1SNrYP1nTQ1qmuFxf1H M/BZtR2Y1VrwrzVtK8VwBdzW054cuXdej8Hpi+qCzK1DkBtRWbveHMmHt/Dgg== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Fix vsetivli instruction asm for IMM AVL Date: Tue, 3 Jan 2023 09:39:57 +0800 Message-Id: <20230103013957.318395-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_ABUSEAT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, RCVD_IN_SBL_CSS, RCVD_IN_XBL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong Notice that we should used vsetivli zero,4 instead of vsetvli zero,4 for IMM AVL (0 ~ 31) according to RVV ISA. This patch fix vsetivli instruction asm bug. gcc/ChangeLog: * config/riscv/vector.md: gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vle-constraint-1.c: --- gcc/config/riscv/vector.md | 2 +- .../gcc.target/riscv/rvv/base/vle-constraint-1.c | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 3d0174f98a2..4e93b7fead5 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -561,7 +561,7 @@ (match_operand 3 "const_int_operand" "i") (match_operand 4 "const_int_operand" "i")] UNSPEC_VSETVL))] "TARGET_VECTOR" - "vsetvli\tzero,%0,e%1,%m2,t%p3,m%p4" + "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4" [(set_attr "type" "vsetvl") (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c index b7cf98bfd9f..8d01e2082f8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c @@ -6,7 +6,7 @@ /* ** f1: -** vsetvli\tzero,4,e32,m1,tu,ma +** vsetivli\tzero,4,e32,m1,tu,ma ** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) ** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) ** vse32\.v\tv[0-9]+,0\([a-x0-9]+\) @@ -23,7 +23,7 @@ void f1 (float * in, float *out) ** f2: ** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** vsetvli\tzero,4,e32,m1,ta,ma +** vsetivli\tzero,4,e32,m1,ta,ma ** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vse32.v\tv[0-9]+,0\([a-x0-9]+\) ** ret @@ -41,7 +41,7 @@ void f2 (float * in, float *out) ** f3: ** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** vsetvli\tzero,4,e32,m1,tu,mu +** vsetivli\tzero,4,e32,m1,tu,mu ** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) ** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vse32.v\tv[0-9]+,0\([a-x0-9]+\) @@ -58,7 +58,7 @@ void f3 (float * in, float *out) /* ** f4: -** vsetvli\tzero,4,e8,mf8,tu,ma +** vsetivli\tzero,4,e8,mf8,tu,ma ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) ** vse8\.v\tv[0-9]+,0\([a-x0-9]+\) @@ -75,7 +75,7 @@ void f4 (int8_t * in, int8_t *out) ** f5: ** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** vsetvli\tzero,4,e8,mf8,ta,ma +** vsetivli\tzero,4,e8,mf8,ta,ma ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vse8.v\tv[0-9]+,0\([a-x0-9]+\) ** ret @@ -93,7 +93,7 @@ void f5 (int8_t * in, int8_t *out) ** f6: ** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** vsetvli\tzero,4,e8,mf8,tu,mu +** vsetivli\tzero,4,e8,mf8,tu,mu ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vse8.v\tv[0-9]+,0\([a-x0-9]+\)