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Thu, 01 Dec 2022 01:36:23 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 2B11aKbs26608326 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 1 Dec 2022 01:36:20 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 98D6EA405C; Thu, 1 Dec 2022 01:36:20 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C522AA4054; Thu, 1 Dec 2022 01:36:19 +0000 (GMT) Received: from pike.rch.stglabs.ibm.com (unknown [9.5.12.127]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 1 Dec 2022 01:36:19 +0000 (GMT) To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org, guojiufu@linux.ibm.com Subject: [PATCH 1/3]rs6000: NFC use more readable pattern to clean high 32 bits Date: Thu, 1 Dec 2022 09:36:17 +0800 Message-Id: <20221201013619.196004-1-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.17.1 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: t_KuLnU4IKTqOueUCdcmc0dxvmjqwAfZ X-Proofpoint-GUID: nilqQd3CUKkKK_DJOQpEx8-vylEyQFNi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-30_04,2022-11-30_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 clxscore=1015 mlxscore=0 bulkscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2212010007 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiufu Guo via Gcc-patches From: Jiufu Guo Reply-To: Jiufu Guo Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, This patch is just using a more readable pattern for "rldicl x,x,0,32" to clean high 32bits. Old pattern looks like: r118:DI=zero_extend(r120:DI#0) new pattern looks like: r118:DI=r120:DI&0xffffffff Bootstrap and regtest pass on ppc64{,le}. Is this ok for trunk? BR, Jeff (Jiufu) gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Update zero_extend(reg:DI#0) to reg:DI&0xffffffff. --- gcc/config/rs6000/rs6000.cc | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index eb7ad5e954f..5efe9b22d8b 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -10267,10 +10267,7 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c) emit_move_insn (copy_rtx (temp), gen_rtx_IOR (DImode, copy_rtx (temp), GEN_INT (ud1))); - emit_move_insn (dest, - gen_rtx_ZERO_EXTEND (DImode, - gen_lowpart (SImode, - copy_rtx (temp)))); + emit_move_insn (dest, gen_rtx_AND (DImode, temp, GEN_INT (0xffffffff))); } else if (ud1 == ud3 && ud2 == ud4) { From patchwork Thu Dec 1 01:36:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiufu Guo X-Patchwork-Id: 1710807 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Thu, 1 Dec 2022 01:36:21 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 96EAFA405B; Thu, 1 Dec 2022 01:36:21 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CCEC3A4054; Thu, 1 Dec 2022 01:36:20 +0000 (GMT) Received: from pike.rch.stglabs.ibm.com (unknown [9.5.12.127]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 1 Dec 2022 01:36:20 +0000 (GMT) To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org, guojiufu@linux.ibm.com Subject: [PATCH 2/3]rs6000: NFC use sext_hwi to replace ((v&0xf..f)^0x80..0) - 0x80..0 Date: Thu, 1 Dec 2022 09:36:18 +0800 Message-Id: <20221201013619.196004-2-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221201013619.196004-1-guojiufu@linux.ibm.com> References: <20221201013619.196004-1-guojiufu@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: ePxBHo_z3R2bvrF6ptYe9DTfprNJ95R6 X-Proofpoint-ORIG-GUID: CQVkT5A1Gn5rFAjPvy3b6TxrmUU7CSts X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-30_04,2022-11-30_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 impostorscore=0 suspectscore=0 bulkscore=0 phishscore=0 spamscore=0 mlxscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2212010007 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiufu Guo via Gcc-patches From: Jiufu Guo Reply-To: Jiufu Guo Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, This patch just uses sext_hwi to replace the expression like: ((value & 0xf..f) ^ 0x80..0) - 0x80..0 for rs6000.cc and rs6000.md. Bootstrap & regtest pass on ppc64{,le}. Is this ok for trunk? BR, Jeff (Jiufu) gcc/ChangeLog: * config/rs6000/rs6000.cc (num_insns_constant_gpr): Use sext_hwi. (darwin_rs6000_legitimate_lo_sum_const_p): Likewise. (mem_operand_gpr): Likewise. (mem_operand_ds_form): Likewise. (rs6000_legitimize_address): Likewise. (rs6000_emit_set_const): Likewise. (rs6000_emit_set_long_const): Likewise. (print_operand): Likewise. * config/rs6000/rs6000.md: Likewise. --- gcc/config/rs6000/rs6000.cc | 30 +++++++++++++----------------- gcc/config/rs6000/rs6000.md | 10 +++++----- 2 files changed, 18 insertions(+), 22 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 5efe9b22d8b..718072cc9a1 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -6021,7 +6021,7 @@ num_insns_constant_gpr (HOST_WIDE_INT value) else if (TARGET_POWERPC64) { - HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; + HOST_WIDE_INT low = sext_hwi (value, 32); HOST_WIDE_INT high = value >> 31; if (high == 0 || high == -1) @@ -8456,7 +8456,7 @@ darwin_rs6000_legitimate_lo_sum_const_p (rtx x, machine_mode mode) } /* We only care if the access(es) would cause a change to the high part. */ - offset = ((offset & 0xffff) ^ 0x8000) - 0x8000; + offset = sext_hwi (offset, 16); return SIGNED_16BIT_OFFSET_EXTRA_P (offset, extra); } @@ -8522,7 +8522,7 @@ mem_operand_gpr (rtx op, machine_mode mode) if (GET_CODE (addr) == LO_SUM) /* For lo_sum addresses, we must allow any offset except one that causes a wrap, so test only the low 16 bits. */ - offset = ((offset & 0xffff) ^ 0x8000) - 0x8000; + offset = sext_hwi (offset, 16); return SIGNED_16BIT_OFFSET_EXTRA_P (offset, extra); } @@ -8562,7 +8562,7 @@ mem_operand_ds_form (rtx op, machine_mode mode) if (GET_CODE (addr) == LO_SUM) /* For lo_sum addresses, we must allow any offset except one that causes a wrap, so test only the low 16 bits. */ - offset = ((offset & 0xffff) ^ 0x8000) - 0x8000; + offset = sext_hwi (offset, 16); return SIGNED_16BIT_OFFSET_EXTRA_P (offset, extra); } @@ -9136,7 +9136,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, { HOST_WIDE_INT high_int, low_int; rtx sum; - low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; + low_int = sext_hwi (INTVAL (XEXP (x, 1)), 16); if (low_int >= 0x8000 - extra) low_int = 0; high_int = INTVAL (XEXP (x, 1)) - low_int; @@ -10203,7 +10203,7 @@ rs6000_emit_set_const (rtx dest, rtx source) lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, DImode); emit_move_insn (hi, GEN_INT (c >> 32)); - c = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000; + c = sext_hwi (c, 32); emit_move_insn (lo, GEN_INT (c)); } else @@ -10242,7 +10242,7 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c) if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000)) || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000))) - emit_move_insn (dest, GEN_INT ((ud1 ^ 0x8000) - 0x8000)); + emit_move_insn (dest, GEN_INT (sext_hwi (ud1, 16))); else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000)) || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000))) @@ -10250,7 +10250,7 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c) temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode); emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest, - GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000)); + GEN_INT (sext_hwi (ud2 << 16, 32))); if (ud1 != 0) emit_move_insn (dest, gen_rtx_IOR (DImode, copy_rtx (temp), @@ -10261,8 +10261,7 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c) temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode); gcc_assert (ud2 & 0x8000); - emit_move_insn (copy_rtx (temp), - GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000)); + emit_move_insn (copy_rtx (temp), GEN_INT (sext_hwi (ud2 << 16, 32))); if (ud1 != 0) emit_move_insn (copy_rtx (temp), gen_rtx_IOR (DImode, copy_rtx (temp), @@ -10273,7 +10272,7 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c) { temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode); HOST_WIDE_INT num = (ud2 << 16) | ud1; - rs6000_emit_set_long_const (temp, (num ^ 0x80000000) - 0x80000000); + rs6000_emit_set_long_const (temp, sext_hwi (num, 32)); rtx one = gen_rtx_AND (DImode, temp, GEN_INT (0xffffffff)); rtx two = gen_rtx_ASHIFT (DImode, temp, GEN_INT (32)); emit_move_insn (dest, gen_rtx_IOR (DImode, one, two)); @@ -10283,8 +10282,7 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c) { temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode); - emit_move_insn (copy_rtx (temp), - GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000)); + emit_move_insn (copy_rtx (temp), GEN_INT (sext_hwi (ud3 << 16, 32))); if (ud2 != 0) emit_move_insn (copy_rtx (temp), gen_rtx_IOR (DImode, copy_rtx (temp), @@ -10336,8 +10334,7 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c) { temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode); - emit_move_insn (copy_rtx (temp), - GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000)); + emit_move_insn (copy_rtx (temp), GEN_INT (sext_hwi (ud4 << 16, 32))); if (ud3 != 0) emit_move_insn (copy_rtx (temp), gen_rtx_IOR (DImode, copy_rtx (temp), @@ -14167,8 +14164,7 @@ print_operand (FILE *file, rtx x, int code) /* If constant, low-order 16 bits of constant, signed. Otherwise, write normally. */ if (INT_P (x)) - fprintf (file, HOST_WIDE_INT_PRINT_DEC, - ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000); + fprintf (file, HOST_WIDE_INT_PRINT_DEC, sext_hwi (INTVAL (x), 16)); else print_operand (file, x, 0); return; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 3bae303086b..4bd1dfd3da9 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1787,7 +1787,7 @@ (define_expand "add3" } HOST_WIDE_INT val = INTVAL (operands[2]); - HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; + HOST_WIDE_INT low = sext_hwi (val, 16); HOST_WIDE_INT rest = trunc_int_for_mode (val - low, mode); if (mode == DImode && !satisfies_constraint_L (GEN_INT (rest))) @@ -1930,7 +1930,7 @@ (define_split (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))] { HOST_WIDE_INT val = INTVAL (operands[2]); - HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; + HOST_WIDE_INT low = sext_hwi (val, 16); HOST_WIDE_INT rest = trunc_int_for_mode (val - low, mode); operands[4] = GEN_INT (low); @@ -8213,7 +8213,7 @@ (define_split operands[2] = operand_subword (operands[0], endian, 0, mode); operands[3] = operand_subword (operands[0], 1 - endian, 0, mode); operands[4] = GEN_INT (value >> 32); - operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); + operands[1] = GEN_INT (sext_hwi (value, 32)); }) (define_split @@ -9577,7 +9577,7 @@ (define_split operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, DImode); operands[4] = GEN_INT (value >> 32); - operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); + operands[1] = GEN_INT (sext_hwi (value, 32)); }) (define_split @@ -12425,7 +12425,7 @@ (define_peephole2 SImode, operands[1], operands[2]); HOST_WIDE_INT c = INTVAL (cnst); - HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; + HOST_WIDE_INT sextc = sext_hwi (c, 16); HOST_WIDE_INT xorv = c ^ sextc; operands[9] = GEN_INT (xorv); From patchwork Thu Dec 1 01:36:19 2022 Content-Type: text/plain; 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Thu, 01 Dec 2022 01:36:24 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06avi18878370.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 2B11b5oo11928214 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 1 Dec 2022 01:37:05 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 94328A4054; Thu, 1 Dec 2022 01:36:22 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CAA59A405C; Thu, 1 Dec 2022 01:36:21 +0000 (GMT) Received: from pike.rch.stglabs.ibm.com (unknown [9.5.12.127]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 1 Dec 2022 01:36:21 +0000 (GMT) To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org, guojiufu@linux.ibm.com Subject: [PATCH 3/3]rs6000: NFC no need copy_rtx in rs6000_emit_set_long_const and rs6000_emit_set_const Date: Thu, 1 Dec 2022 09:36:19 +0800 Message-Id: <20221201013619.196004-3-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221201013619.196004-1-guojiufu@linux.ibm.com> References: <20221201013619.196004-1-guojiufu@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: XWysbaztaOKR0PUdtxP8mnL-I8R8gn8s X-Proofpoint-GUID: rRfW7rqKhQXTX65qG9NlyJ0GpjhTnE0b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-30_04,2022-11-30_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 priorityscore=1501 suspectscore=0 mlxscore=0 clxscore=1015 spamscore=0 malwarescore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2212010007 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiufu Guo via Gcc-patches From: Jiufu Guo Reply-To: Jiufu Guo Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, Function rs6000_emit_set_const/rs6000_emit_set_long_const are only invoked from two "define_split"s where the target operand is limited to gpc_reg_operand or int_reg_operand, then the operand must be REG_P. And in rs6000_emit_set_const/rs6000_emit_set_long_const, to create temp rtx, it is using code like "gen_reg_rtx({S|D}Imode)", it must also be REG_P. So, copy_rtx is not needed for temp and dest. This patch removes those "copy_rtx" for rs6000_emit_set_const and rs6000_emit_set_long_const. Bootstrap & regtest pass on ppc64{,le}. Is this ok for trunk? BR, Jeff (Jiufu) gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_set_const): Remove copy_rtx. (rs6000_emit_set_long_const): Likewise. --- gcc/config/rs6000/rs6000.cc | 58 +++++++++++++------------------------ 1 file changed, 20 insertions(+), 38 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 718072cc9a1..1a51b79ebfe 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -10186,10 +10186,9 @@ rs6000_emit_set_const (rtx dest, rtx source) case E_SImode: temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode); - emit_insn (gen_rtx_SET (copy_rtx (temp), - GEN_INT (c & ~(HOST_WIDE_INT) 0xffff))); + emit_insn (gen_rtx_SET (temp, GEN_INT (c & ~(HOST_WIDE_INT) 0xffff))); emit_insn (gen_rtx_SET (dest, - gen_rtx_IOR (SImode, copy_rtx (temp), + gen_rtx_IOR (SImode, temp, GEN_INT (c & 0xffff)))); break; @@ -10198,10 +10197,8 @@ rs6000_emit_set_const (rtx dest, rtx source) { rtx hi, lo; - hi = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN == 0, - DImode); - lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, - DImode); + hi = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, DImode); + lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, DImode); emit_move_insn (hi, GEN_INT (c >> 32)); c = sext_hwi (c, 32); emit_move_insn (lo, GEN_INT (c)); @@ -10249,23 +10246,19 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c) { temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode); - emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest, + emit_move_insn (ud1 != 0 ? temp : dest, GEN_INT (sext_hwi (ud2 << 16, 32))); if (ud1 != 0) - emit_move_insn (dest, - gen_rtx_IOR (DImode, copy_rtx (temp), - GEN_INT (ud1))); + emit_move_insn (dest, gen_rtx_IOR (DImode, temp, GEN_INT (ud1))); } else if (ud3 == 0 && ud4 == 0) { temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode); gcc_assert (ud2 & 0x8000); - emit_move_insn (copy_rtx (temp), GEN_INT (sext_hwi (ud2 << 16, 32))); + emit_move_insn (temp, GEN_INT (sext_hwi (ud2 << 16, 32))); if (ud1 != 0) - emit_move_insn (copy_rtx (temp), - gen_rtx_IOR (DImode, copy_rtx (temp), - GEN_INT (ud1))); + emit_move_insn (temp, gen_rtx_IOR (DImode, temp, GEN_INT (ud1))); emit_move_insn (dest, gen_rtx_AND (DImode, temp, GEN_INT (0xffffffff))); } else if (ud1 == ud3 && ud2 == ud4) @@ -10282,18 +10275,13 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c) { temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode); - emit_move_insn (copy_rtx (temp), GEN_INT (sext_hwi (ud3 << 16, 32))); + emit_move_insn (temp, GEN_INT (sext_hwi (ud3 << 16, 32))); if (ud2 != 0) - emit_move_insn (copy_rtx (temp), - gen_rtx_IOR (DImode, copy_rtx (temp), - GEN_INT (ud2))); - emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest, - gen_rtx_ASHIFT (DImode, copy_rtx (temp), - GEN_INT (16))); + emit_move_insn (temp, gen_rtx_IOR (DImode, temp, GEN_INT (ud2))); + emit_move_insn (ud1 != 0 ? temp : dest, + gen_rtx_ASHIFT (DImode, temp, GEN_INT (16))); if (ud1 != 0) - emit_move_insn (dest, - gen_rtx_IOR (DImode, copy_rtx (temp), - GEN_INT (ud1))); + emit_move_insn (dest, gen_rtx_IOR (DImode, temp, GEN_INT (ud1))); } else if (TARGET_PREFIXED) { @@ -10334,23 +10322,17 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c) { temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode); - emit_move_insn (copy_rtx (temp), GEN_INT (sext_hwi (ud4 << 16, 32))); + emit_move_insn (temp, GEN_INT (sext_hwi (ud4 << 16, 32))); if (ud3 != 0) - emit_move_insn (copy_rtx (temp), - gen_rtx_IOR (DImode, copy_rtx (temp), - GEN_INT (ud3))); + emit_move_insn (temp, gen_rtx_IOR (DImode, temp, GEN_INT (ud3))); - emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest, - gen_rtx_ASHIFT (DImode, copy_rtx (temp), - GEN_INT (32))); + emit_move_insn (ud2 != 0 || ud1 != 0 ? temp : dest, + gen_rtx_ASHIFT (DImode, temp, GEN_INT (32))); if (ud2 != 0) - emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest, - gen_rtx_IOR (DImode, copy_rtx (temp), - GEN_INT (ud2 << 16))); + emit_move_insn (ud1 != 0 ? temp : dest, + gen_rtx_IOR (DImode, temp, GEN_INT (ud2 << 16))); if (ud1 != 0) - emit_move_insn (dest, - gen_rtx_IOR (DImode, copy_rtx (temp), - GEN_INT (ud1))); + emit_move_insn (dest, gen_rtx_IOR (DImode, temp, GEN_INT (ud1))); } }