From patchwork Wed Nov 23 14:07:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1708315 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=mGwjBruv; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NHNJ56L1qz23mf for ; Thu, 24 Nov 2022 01:08:04 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AD4D6851F5; Wed, 23 Nov 2022 15:07:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mGwjBruv"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9B1F5852B6; Wed, 23 Nov 2022 15:07:56 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.9 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, SPF_HELO_NONE,SPF_NONE autolearn=no autolearn_force=no version=3.4.2 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 688B0851CB for ; Wed, 23 Nov 2022 15:07:53 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669212473; x=1700748473; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=55IleZ/ymMtmZggVPXIqOTK8Ijl0hpAwBODJ86l9Ex0=; b=mGwjBruv8adMRHyqiQvCL/T+TpkLtX9bcLYpx1mYpgNythfN+NaW4ub6 lguGLuQAZEeuuXX8QCi5ayVqdZmmfL0AsXSrCBsBUsD6mQ2l1JWHT2l8j /YKgFBcHlNQlx0MzgjTO7UETu0jSIlVbSW3Dw/PTU5k9ixHusXEoqsovD AHcw+ekKdseNnzXJoavTHirqCTdai+dtJqMbwHU90n73PDPKSV2UhO+YT i2y/BsDNE+37RAAT8U/1riLjYtmLtHEc8ej1UC93u2sVUIfSnGMROWLCJ oUqyB5v5xrqAdpez81D7eN/1cfXlVXsbhualkx11ux4USBnb/Lwq2jax9 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="400364710" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="400364710" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2022 06:07:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="641808330" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="641808330" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga002.jf.intel.com with ESMTP; 23 Nov 2022 06:07:22 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id DEA42482B; Wed, 23 Nov 2022 22:07:21 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id D3402E0095B; Wed, 23 Nov 2022 22:07:21 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Ley Foon Tan Subject: [PATCH 1/2] arm: socfpga: soc64: Add mask support when enable/disable bridges Date: Wed, 23 Nov 2022 22:07:19 +0800 Message-Id: <20221123140720.31941-1-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Ley Foon Tan HSD #18016042797-1: The existing ignore the "mask" value when call to socfpga_bridges_reset(). This patch add the mask support when bridge enable/disable. Mask value: BIT0: soc2fpga BIT1: lwhps2fpga BIT2: fpga2soc These bridges available only in Stratix 10: BIT3: f2sdram0 BIT4: f2sdram1 BIT5: f2sdram2 Signed-off-by: Ley Foon Tan Signed-off-by: Jit Loon Lim --- .../include/mach/reset_manager_soc64.h | 9 +- arch/arm/mach-socfpga/misc_soc64.c | 2 +- arch/arm/mach-socfpga/reset_manager_s10.c | 154 +++++++++++------- 3 files changed, 101 insertions(+), 64 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index 9589b61749..b662b4450d 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -9,7 +9,8 @@ void reset_deassert_peripherals_handoff(void); int cpu_has_been_warmreset(void); void print_reset_info(void); -void socfpga_bridges_reset(int enable); +void socfpga_bridges_reset(int enable, unsigned int mask); +void socfpga_bridges_reset_psci(int enable, unsigned int mask); #define RSTMGR_SOC64_STATUS 0x00 #define RSTMGR_SOC64_HDSKEN 0x10 @@ -29,12 +30,6 @@ void socfpga_bridges_reset(int enable); #define RSTMGR_BRGMODRST_F2SDRAM1_MASK BIT(4) #define RSTMGR_BRGMODRST_F2SDRAM2_MASK BIT(5) #define RSTMGR_BRGMODRST_DDRSCH_MASK BIT(6) -#define BRGMODRST_SOC2FPGA_BRIDGES (RSTMGR_BRGMODRST_SOC2FPGA_MASK | \ - RSTMGR_BRGMODRST_LWSOC2FPGA_MASK) -#define BRGMODRST_FPGA2SOC_BRIDGES (RSTMGR_BRGMODRST_FPGA2SOC_MASK | \ - RSTMGR_BRGMODRST_F2SDRAM0_MASK | \ - RSTMGR_BRGMODRST_F2SDRAM1_MASK | \ - RSTMGR_BRGMODRST_F2SDRAM2_MASK) #define RSTMGR_HDSKEN_FPGAHSEN BIT(2) #define RSTMGR_HDSKREQ_FPGAHSREQ BIT(2) diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index 2acdfad07b..49b241b7b8 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -87,5 +87,5 @@ void do_bridge_reset(int enable, unsigned int mask) return; } - socfpga_bridges_reset(enable); + socfpga_bridges_reset(enable, mask); } diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index 0274c4dbdb..128cdbbbe3 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -24,30 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; #define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50 #define F2SDRAM_SIDEBAND_FLAGOUTCLR0 0x54 -#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 -#define FLAGINSTATUS0_MPFE_NOC_IDLE (BIT(0) | BIT(4) | BIT(8)) -#define FLAGINSTATUS0_MPFE_NOC_IDLEACK (BIT(1) | BIT(5) | BIT(9)) -#define FLAGINSTATUS0_F2S_CMD_EMPTY (BIT(2) | BIT(6) | BIT(10)) -#define FLAGINSTATUS0_F2S_RESP_EMPTY (BIT(3) | BIT(7) | BIT(11)) - -#define FLGAOUTSET0_MPFE_NOC_IDLEREQ (BIT(0) | BIT(3) | BIT(6)) -#define FLGAOUTSET0_F2S_EN (BIT(1) | BIT(4) | BIT(7)) -#define FLGAOUTSET0_F2S_FORCE_DRAIN (BIT(2) | BIT(5) | BIT(8)) - -#define FLGAOUTCLR0_F2S_IDLEREQ (BIT(0) | BIT(3) | BIT(6)) -#else -#define FLAGINSTATUS0_MPFE_NOC_IDLE BIT(0) -#define FLAGINSTATUS0_MPFE_NOC_IDLEACK BIT(1) -#define FLAGINSTATUS0_F2S_CMD_EMPTY BIT(2) -#define FLAGINSTATUS0_F2S_RESP_EMPTY BIT(3) - -#define FLGAOUTSET0_MPFE_NOC_IDLEREQ BIT(0) -#define FLGAOUTSET0_F2S_EN BIT(1) -#define FLGAOUTSET0_F2S_FORCE_DRAIN BIT(2) - -#define FLGAOUTCLR0_F2S_IDLEREQ BIT(0) -#endif - #define POLL_FOR_ZERO(expr, timeout_ms) \ { \ int timeout = (timeout_ms); \ @@ -110,26 +86,79 @@ void socfpga_per_reset_all(void) writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST); } -static __always_inline void socfpga_f2s_bridges_reset(int enable) +static __always_inline void socfpga_f2s_bridges_reset(int enable, + unsigned int mask) { int timeout_ms = 300; u32 empty; + u32 brg_mask; + u32 flagout_idlereq = 0; + u32 flagoutset_fdrain = 0; + u32 flagoutset_en = 0; + u32 flaginstatus_idleack = 0; + u32 flaginstatus_respempty = 0; + + if (CONFIG_IS_ENABLED(TARGET_SOCFPGA_STRATIX10)) { + /* Support fpga2soc and f2sdram */ + brg_mask = mask & (RSTMGR_BRGMODRST_FPGA2SOC_MASK | + RSTMGR_BRGMODRST_F2SDRAM0_MASK | + RSTMGR_BRGMODRST_F2SDRAM1_MASK | + RSTMGR_BRGMODRST_F2SDRAM2_MASK); + + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM0_MASK) { + flagout_idlereq |= BIT(0); + flaginstatus_idleack |= BIT(1); + flagoutset_fdrain |= BIT(2); + flagoutset_en |= BIT(1); + flaginstatus_respempty |= BIT(3); + } + + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM1_MASK) { + flagout_idlereq |= BIT(3); + flaginstatus_idleack |= BIT(5); + flagoutset_fdrain |= BIT(5); + flagoutset_en |= BIT(4); + flaginstatus_respempty |= BIT(7); + } + + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM2_MASK) { + flagout_idlereq |= BIT(6); + flaginstatus_idleack |= BIT(9); + flagoutset_fdrain |= BIT(8); + flagoutset_en |= BIT(7); + flaginstatus_respempty |= BIT(11); + } + } else { + /* Support fpga2soc only */ + brg_mask = mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK; + if (brg_mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK) { + flagout_idlereq |= BIT(0); + flaginstatus_idleack |= BIT(1); + flagoutset_fdrain |= BIT(2); + flagoutset_en |= BIT(1); + flaginstatus_respempty |= BIT(3); + } + } + + /* mask is not set, return here */ + if (!brg_mask) + return; if (enable) { clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - BRGMODRST_FPGA2SOC_BRIDGES); + brg_mask); clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGOUTSET0, - FLGAOUTSET0_MPFE_NOC_IDLEREQ); + flagout_idlereq); POLL_FOR_ZERO((readl(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGINSTATUS0) & - FLAGINSTATUS0_MPFE_NOC_IDLEACK), timeout_ms); + flaginstatus_idleack), timeout_ms); clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGOUTSET0, - FLGAOUTSET0_F2S_FORCE_DRAIN); + flagoutset_fdrain); setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + - F2SDRAM_SIDEBAND_FLAGOUTSET0, FLGAOUTSET0_F2S_EN); + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_en); __socfpga_udelay(1); /* wait 1us */ } else { @@ -140,11 +169,11 @@ static __always_inline void socfpga_f2s_bridges_reset(int enable) POLL_FOR_SET(readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKACK), timeout_ms); clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + - F2SDRAM_SIDEBAND_FLAGOUTSET0, FLGAOUTSET0_F2S_EN); + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_en); __socfpga_udelay(1); setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGOUTSET0, - FLGAOUTSET0_F2S_FORCE_DRAIN); + flagoutset_fdrain); __socfpga_udelay(1); do { @@ -154,11 +183,11 @@ static __always_inline void socfpga_f2s_bridges_reset(int enable) */ empty = readl(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGINSTATUS0) & - FLAGINSTATUS0_F2S_RESP_EMPTY; + flaginstatus_respempty; if (empty) { empty = readl(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGINSTATUS0) & - FLAGINSTATUS0_F2S_RESP_EMPTY; + flaginstatus_respempty; if (empty) break; } @@ -168,60 +197,73 @@ static __always_inline void socfpga_f2s_bridges_reset(int enable) } while (timeout_ms); setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - BRGMODRST_FPGA2SOC_BRIDGES & - ~RSTMGR_BRGMODRST_FPGA2SOC_MASK); + brg_mask & ~RSTMGR_BRGMODRST_FPGA2SOC_MASK); clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ, RSTMGR_HDSKREQ_FPGAHSREQ); setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGOUTCLR0, - FLGAOUTCLR0_F2S_IDLEREQ); + flagout_idlereq); } } -static __always_inline void socfpga_s2f_bridges_reset(int enable) +static __always_inline void socfpga_s2f_bridges_reset(int enable, + unsigned int mask) { + unsigned int noc_mask = 0; + unsigned int brg_mask = 0; + + if (mask & RSTMGR_BRGMODRST_SOC2FPGA_MASK) { + noc_mask = SYSMGR_NOC_H2F_MSK; + brg_mask = RSTMGR_BRGMODRST_SOC2FPGA_MASK; + } + + if (mask & RSTMGR_BRGMODRST_LWSOC2FPGA_MASK) { + noc_mask |= SYSMGR_NOC_LWH2F_MSK; + brg_mask |= RSTMGR_BRGMODRST_LWSOC2FPGA_MASK; + } + + /* s2f mask is not set, return here */ + if (!brg_mask) + return; + if (enable) { /* clear idle request to all bridges */ setbits_le32(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0); + SYSMGR_SOC64_NOC_IDLEREQ_CLR, noc_mask); /* Release SOC2FPGA bridges from reset state */ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - BRGMODRST_SOC2FPGA_BRIDGES); + brg_mask); /* Poll until all idleack to 0 */ POLL_FOR_ZERO(readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_IDLEACK), 300); } else { /* set idle request to all bridges */ - writel(~0, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEREQ_SET); + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEREQ_SET, noc_mask); /* Enable the NOC timeout */ writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); /* Poll until all idleack to 1 */ POLL_FOR_ZERO(readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEACK) ^ - (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK), - 300); + SYSMGR_SOC64_NOC_IDLEACK) ^ noc_mask, 300); POLL_FOR_ZERO(readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLESTATUS) ^ - (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK), + SYSMGR_SOC64_NOC_IDLESTATUS) ^ noc_mask, 300); - /* Reset all SOC2FPGA bridges (except NOR DDR scheduler & F2S) */ + /* Reset SOC2FPGA bridges */ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - BRGMODRST_SOC2FPGA_BRIDGES); + brg_mask); /* Disable NOC timeout */ writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); } } -void socfpga_bridges_reset(int enable) +void socfpga_bridges_reset(int enable, unsigned int mask) { if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) { u64 arg = enable; @@ -233,15 +275,15 @@ void socfpga_bridges_reset(int enable) printf("Failed to %s the HPS bridges, error %d\n", enable ? "enable" : "disable", ret); } else { - socfpga_s2f_bridges_reset(enable); - socfpga_f2s_bridges_reset(enable); + socfpga_s2f_bridges_reset(enable, mask); + socfpga_f2s_bridges_reset(enable, mask); } } -void __secure socfpga_bridges_reset_psci(int enable) +void __secure socfpga_bridges_reset_psci(int enable, unsigned int mask) { - socfpga_s2f_bridges_reset(enable); - socfpga_f2s_bridges_reset(enable); + socfpga_s2f_bridges_reset(enable, mask); + socfpga_f2s_bridges_reset(enable, mask); } /* From patchwork Wed Nov 23 14:07:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1708316 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Wed, 23 Nov 2022 22:07:22 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 52702E0095B; Wed, 23 Nov 2022 22:07:22 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Ley Foon Tan Subject: [PATCH 2/2] arm: socfpga: soc64: Add mask support to INTEL_SIP_SMC_HPS_SET_BRIDGES Date: Wed, 23 Nov 2022 22:07:20 +0800 Message-Id: <20221123140720.31941-2-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20221123140720.31941-1-jit.loon.lim@intel.com> References: <20221123140720.31941-1-jit.loon.lim@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Ley Foon Tan HSD #18016042797-2: Add mask support to INTEL_SIP_SMC_HPS_SET_BRIDGES SMC call. Signed-off-by: Ley Foon Tan Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/reset_manager_s10.c | 10 +++++++--- include/linux/intel-smc.h | 14 ++++++++++---- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index 128cdbbbe3..bc643218d2 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -266,11 +266,15 @@ static __always_inline void socfpga_s2f_bridges_reset(int enable, void socfpga_bridges_reset(int enable, unsigned int mask) { if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) { - u64 arg = enable; + u64 arg[2]; int ret; - ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, - 0); + /* Set bit-1 to indicate has mask value in arg[1]. */ + arg[0] = (enable & BIT(0)) | BIT(1); + arg[1] = mask; + + ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, arg, + ARRAY_SIZE(arg), NULL, 0); if (ret) printf("Failed to %s the HPS bridges, error %d\n", enable ? "enable" : "disable", ret); diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h index a54eff43ad..e15fa3d4da 100644 --- a/include/linux/intel-smc.h +++ b/include/linux/intel-smc.h @@ -482,10 +482,16 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) * Call register usage: * a0 INTEL_SIP_SMC_HPS_SET_BRIDGES * a1 Set bridges status: - * 0 - Disable - * 1 - Enable - * a2-7 not used - * + * Bit 0: 0 - Disable, 1 - Enable + * Bit 1: 1 - Has mask value in a2 + * a2 Mask value + * Bit 0: soc2fpga + * Bit 1: lwhps2fpga + * Bit 2: fpga2soc + * Bit 3: f2sdram0 (For Stratix 10 only) + * Bit 4: f2sdram1 (For Stratix 10 only) + * Bit 5: f2sdram2 (For Stratix 10 only) + * a3-7 not used * Return status * a0 INTEL_SIP_SMC_STATUS_OK */