From patchwork Tue Nov 15 11:49:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 1703987 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=O724XnSb; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NBPcx3LwHz23mH for ; Tue, 15 Nov 2022 22:50:25 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0680384FFA; Tue, 15 Nov 2022 12:50:16 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="O724XnSb"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 62EDE85004; Tue, 15 Nov 2022 12:50:14 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4FEF580A46 for ; Tue, 15 Nov 2022 12:50:07 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=d-gole@ti.com Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AFBnusw027876; Tue, 15 Nov 2022 05:49:56 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1668512996; bh=wkV9gdD3YxyRGb58N9YTwsU+Li4MnAil0y5T8GylMSE=; h=From:To:CC:Subject:Date; b=O724XnSbs5U63AWz1wFUlD7BSRdHNdLLebH8NbzPreV2kZDA1sPyly+YfMubFcqb7 4Rztxmzwjbqh1M91p4Px90vaYKcvaJhibk3UOMqj3Qc/O339INbervPjRXQPeEzoTh EZrgez59rLKCmHV+i1bKYqkcGYNxpmlgNCkjhOJc= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AFBnufF026791 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 15 Nov 2022 05:49:56 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 15 Nov 2022 05:49:56 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 15 Nov 2022 05:49:56 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AFBntZU106520; Tue, 15 Nov 2022 05:49:55 -0600 From: Dhruva Gole To: Tom Rini CC: Dhruva Gole , Vignesh , Jagan Teki , , Pratyush Yadav Subject: [PATCH v2 1/2] spi: cadence_qspi: setup ADDR Bits in cmd reads Date: Tue, 15 Nov 2022 17:19:25 +0530 Message-ID: <20221115114926.174351-1-d-gole@ti.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Setup the Addr bit field while issuing register reads in STIG mode. This is needed for example flashes like cypress define in their transaction table that to read any register there is 1 cmd byte and a few more address bytes trailing the cmd byte. Absence of addr bytes will obviously fail to read correct data from flash register that maybe requested by flash driver because the controller doesn't even specify which address of the flash register the read is being requested from. Signed-off-by: Dhruva Gole --- I was trying to use STIG mode to read flash register on my cypress QSPI Flash. However the value that I kept reading back was 0xff and it looked highly sus. This caused the spi-nor core to _THINK_ that okay the register has all the necessary bits that I care about to put the flash in QUAD mode already set, so... I Wont do ANYTHING further to make the flash go into QUAD mode. However this obviously was not the case and the flash was never really going into Quad SPI mode read. Thus when I issued any ``sf read`` then I ended up with just 0xffs and 0x00s and basically non sense data. After actually dumping the STIG register and going into cqspi_apb driver I came to know that in STIG mode we do not support any SPI transactions that may involve additional address bytes after cmd. After this patch, and the one following, I tested sf reads on my AM625 SK EVM and now I get valid reads in Quad SPI mode. I added a few of my own logs: ~~~ => sf read $loadaddr 0x0 0x10000 device 0 offset 0x0, size 0x10000 jedec_spi_nor flash@0: from 0x00000000, len 65536 [..] mylogs: cadence_qspi_set_protocol L#137 data.buswidth = 4 [..] myl: cadence_qspi_apb_read_execute#761 len = 65536 SF: 65536 bytes @ 0x0 Read: OK => md.w $loadaddr 82000000: 8230 9404 8230 fd03 03a0 0102 0202 5214 0...0..........R [...] 82000060: 2731 2530 0306 0455 0c0a 541e 7865 7361 1'0%..U....Texas [...] 82000070: 4920 736e 7274 6d75 6e65 7374 4920 636e Instruments Inc ~~~ This confirms that the read back has the same data I had flashed and it was also read back in Quad mode. drivers/spi/cadence_qspi_apb.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index cfae5dcbda0e..58592daa46aa 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -479,6 +479,28 @@ int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv, /* 0 means 1 byte. */ reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); + + /* setup ADDR BIT field */ + if (op->addr.nbytes) { + writel(op->addr.val, priv->regbase + CQSPI_REG_CMDADDRESS); + /* + * According to the controller register description, + * Number of Address Bytes: Set to the number of address bytes + * required [the address itself is programmed in the FLASH + * COMMAND ADDRESS REGISTERS]. This should be setup before + * triggering the command via bit 0 of this register. + * 00 : 1 address byte + * 01 : 2 address bytes + * 10 : 3 address bytes + * 11 : 4 address bytes + * Hence, subtract 1 from actual addr.nbytes to follow above + * spec + */ + reg |= (op->addr.nbytes - 1) << + CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; + reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); + } + status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg); if (status != 0) return status; From patchwork Tue Nov 15 11:49:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 1703988 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=j2tf0dyJ; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NBPd52CXjz23mY for ; Tue, 15 Nov 2022 22:50:33 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BE7B98503A; Tue, 15 Nov 2022 12:50:19 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="j2tf0dyJ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BA6D480A46; Tue, 15 Nov 2022 12:50:15 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5E96284FB3 for ; Tue, 15 Nov 2022 12:50:09 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=d-gole@ti.com Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AFBnwLS027935; Tue, 15 Nov 2022 05:49:58 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1668512998; bh=ml/aKjevl6eu2WfZqg5f3pea0/TCoqvWHHWeR60wDHo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=j2tf0dyJ3oZhvCKUpIZNMCabTlHvIVzMT+KdfmR4gJLMLAdTtYp6Yv6vL0UPzIGDQ qlVBDDEeybI7DKH2Q/Io+ammq5ck9UWN2ip4nu2gFaCkU9FPziVqO+RE+fgXubuSr/ bCrWzfGB5uYgQGnK2rq7hRJyhhZgezRAD5cnMIe0= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AFBnwwx109192 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 15 Nov 2022 05:49:58 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 15 Nov 2022 05:49:58 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 15 Nov 2022 05:49:58 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AFBnvaA018411; Tue, 15 Nov 2022 05:49:57 -0600 From: Dhruva Gole To: Tom Rini CC: Dhruva Gole , Vignesh , Jagan Teki , , Pratyush Yadav Subject: [PATCH v2 2/2] spi: cadence_qspi: use STIG mode for small reads Date: Tue, 15 Nov 2022 17:19:26 +0530 Message-ID: <20221115114926.174351-2-d-gole@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221115114926.174351-1-d-gole@ti.com> References: <20221115114926.174351-1-d-gole@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Fix the issue where some flash chips like cypress S25HS256T for example return the value of the same register once a SPI transaction starts. So for example if read reg of 0x2 is requested and we start reading registers in DAC mode we start reading 4 byte aligned ie. 0x0, 0x1, 0x2 and then 0x3. In such a case the flash chip keeps returning the value of 0x0 even though we actually want the value of 0x2. STIG mode solves the above issue by not issuing a read continuosly for 4 byte aligned data. Signed-off-by: Dhruva Gole --- v2: No changes from previous patch. However this DEPENDS on PATCH 1/2 of the same series. Hence disregard the previously sent patch: [PATCH] spi: cadence-qspi: use STIG mode for small reads https://lore.kernel.org/u-boot/20221111110720.283013-1-d-gole@ti.com/T/#u drivers/spi/cadence_qspi.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index ab0a681c8376..6f2924fe4515 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -307,7 +307,22 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, priv->is_decoded_cs); if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { - if (!op->addr.nbytes) + /* + * In some cases there is a layer of digital logic in front of the QSPI + * /OSPI Driver when used in DAC mode. This digital logic layer ensures + * that even if we are trying to read 1 or 2 bytes of data, it will + * always align it to 4 bytes from a 4byte aligned address. In some + * flash chips like cypress for example, if we try to read some regs + * in DAC mode then it keeps sending the value of the first register + * who was requested and inorder to read the next register we have to + * stop and re-initiate a new transaction. + * This causes wrong registers values to be read than what is desired + * when registers are read in DAC mode. Hence if the data.nbytes + * is very less then do not use DAC mode. Registers are generally only + * 1-2 bytes and thus switching to STIG mode will be a work around. + */ + if (!op->addr.nbytes || + op->data.nbytes < CQSPI_STIG_DATA_LEN_MAX) mode = CQSPI_STIG_READ; else mode = CQSPI_READ;