From patchwork Mon Nov 7 14:07:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1700680 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=ZqMemXtp; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N5Y3c2KfLz23lT for ; Tue, 8 Nov 2022 01:08:10 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5CC6980431; Mon, 7 Nov 2022 15:07:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ZqMemXtp"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3771380705; Mon, 7 Nov 2022 15:07:57 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B381B80079 for ; Mon, 7 Nov 2022 15:07:53 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667830073; x=1699366073; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=bBxLwAi7h3N/Wc8wWtP+w+AXb5jv4P8PIpVwptkJEQY=; b=ZqMemXtpTavPtL7FvfRPAxCY0NQYFaAB982FD/aC9Z/p4hgaYRVSGIn9 IjEgl88MkEAtaygI6TN+ElQfeIrQdnehuFDIt0Rpsu8ltD4PHN24qHmZs C4nys6OCn57wfmp3MfsbXw9HPDBzoByXG/Bk0wdKurdninNSS0Uml3p2J 057k/VEJ1LXhLPZXWMo80FhzF82hT8qbpdxv9n45z72dUurdFkdUlEsG4 kpwm9pdW0hMNVCX5Mr9JYJTSiKI/N5XAYxdTi8tjjBOE7Tw61cUPFSWAN hDylrtQmw9mdydQzfBICeRI7SDMZ+0iV1wFTJGTypBLfaCu5URc80xyzt w==; X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="310417473" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="310417473" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2022 06:07:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10524"; a="586979172" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="586979172" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga003.jf.intel.com with ESMTP; 07 Nov 2022 06:07:38 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id D43404837; Mon, 7 Nov 2022 22:07:37 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id A33BCE00214; Mon, 7 Nov 2022 22:07:37 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang Subject: [PATCH] Clear previous CPU release address when reset Date: Mon, 7 Nov 2022 22:07:35 +0800 Message-Id: <20221107140735.992-1-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Siew Chin Lim HSD #18013461252: CPU release address is stored in system manager boot scratch register.This patch fixes the CPU crash issue during cold reset in ATF boot flow for Diamond Mesa device. In Diamond Mesa device, boot scratch register will be cleared on POR only. In ATF boot flow, when a cold reset happen on Diamond Mesa device, the boot scratch register still contains previous CPU release address which point to ATF firmware. When primary and secondary core executions reaches lowlevel_init function, it will jump to previous CPU release address and causes crash. This patch will clear the previous CPU release address if the core is reset by cold reset, warm reset or watchdog reset. Signed-off-by: Siew Chin Lim Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/lowlevel_init_soc64.S | 51 +++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S index 875927cc4d..7b37b6eeef 100644 --- a/arch/arm/mach-socfpga/lowlevel_init_soc64.S +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -14,6 +14,55 @@ ENTRY(lowlevel_init) #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + + /* + * In ATF flow, need to clear the old CPU address when cold reset + * being triggered, but shouldn't clear CPU address if it is reset + * by CPU-ON, so that the core can correctly jump to ATF code after + * reset by CPU-ON. CPU-ON trigger the reset via mpumodrst. + * + * Hardware will set 1 to core*_irq in mpurststat register in + * reset manager if the core is reset by mpumodrst. + * + * The following code will check the mpurststat to identify if the + * core is reset by mpumodrst, and it will skip CPU address clearing + * if the core is reset by mpumodrst. At last, the code need to clear + * the core*_irq by set it to 1. So that it can reflect the correct + * and latest status in next reset. + */ + + /* Retrieve mpurststat register in reset manager */ + ldr x4, =SOCFPGA_RSTMGR_ADDRESS + ldr w5, [x4, #0x04] + + /* Set mask based on current core id */ + mrs x0, mpidr_el1 + and x1, x0, #0xF + ldr x2, =0x00000100 + lsl x2, x2, x1 + + /* Skip if core*_irq register is set */ + and x6, x5, x2 + cbnz x6, skip_clear_cpu_address + + /* + * Reach here means core*_irq is 0, means the core is + * reset by cold, warm or watchdog reset. + * Clear previous CPU release address + */ + ldr x4, =CPU_RELEASE_ADDR + str wzr, [x4] + b skip_clear_core_irq + +skip_clear_cpu_address: + /* Clear core*_irq register by writing 1 */ + ldr x4, =SOCFPGA_RSTMGR_ADDRESS + str w2, [x4, #0x04] + +skip_clear_core_irq: + /* Master CPU (CPU0) does not need to wait for atf */ + branch_if_master x0, x1, master_cpu + wait_for_atf: ldr x4, =CPU_RELEASE_ADDR ldr x5, [x4] @@ -21,6 +70,8 @@ wait_for_atf: br x5 slave_wait_atf: branch_if_slave x0, wait_for_atf + +master_cpu: #else branch_if_slave x0, 1f #endif