From patchwork Mon Nov 7 13:33:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1700647 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=FNziGUQ5; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N5XJq6h1fz23lb for ; Tue, 8 Nov 2022 00:34:35 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F264684F2C; Mon, 7 Nov 2022 14:34:31 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="FNziGUQ5"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0C92684F2C; Mon, 7 Nov 2022 14:34:30 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 607E480431 for ; Mon, 7 Nov 2022 14:34:26 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667828066; x=1699364066; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=jmcGCemp9cmObXIyIBAbWonWSjH9fwmymcUFSPE6xaU=; b=FNziGUQ51Qf1Xy6XkuRHPFjdMseUJHmqMbeXQ8YEflm4KL6qiACr2XO9 mpVawJAkAuw+xTBk25j8LhIft9OcCRzYZnK5+xbm11JVI19nuza8pPkTR LR97D/RjzyogdlcdRWoR0T4hC/NlC8bRjeyZcYVO7ihw2EdNE/mTtyh0p mFHrnx4QsQgdsLhxZdgojDVoEv/WuoLEImj7QceTWg92MPxUvocqd+2UG Ft4EIRVcHgNAhLE4VTw79Sf17Qk/Qdw4lLMG1lwtymh1Ygb3QEKL8CWRz YuIWu5pD1Qn9+a9IuKyYJlXCmq+XBuhGV+lX0zGWSklLRgdyOoivv4A2S w==; X-IronPort-AV: E=McAfee;i="6500,9779,10523"; a="290795816" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="290795816" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2022 05:34:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10523"; a="725138770" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="725138770" Received: from pglmail07.png.intel.com ([10.221.193.207]) by FMSMGA003.fm.intel.com with ESMTP; 07 Nov 2022 05:34:19 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id 403434837; Mon, 7 Nov 2022 21:34:19 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 3EF92E00214; Mon, 7 Nov 2022 21:34:19 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Ley Foon Tan Subject: [PATCH 1/3] fpga: intel_pr: Change to use fdt_get_resource() Date: Mon, 7 Nov 2022 21:33:49 +0800 Message-Id: <20221107133351.26311-1-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Ley Foon Tan HSD #1508201592: Change from fdtdec_get_addr() to fdt_get_resource(). fdtdec_get_addr() returns a 64-bit value, including base address and register size. Change to use fdt_get_resource() and get base address from struct fdt_resource. Signed-off-by: Ley Foon Tan Signed-off-by: Jit Loon Lim --- drivers/fpga/intel_pr.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/fpga/intel_pr.c b/drivers/fpga/intel_pr.c index b8f510fbd7..6637425452 100644 --- a/drivers/fpga/intel_pr.c +++ b/drivers/fpga/intel_pr.c @@ -34,6 +34,8 @@ static int intel_get_freeze_br_addr(fdt_addr_t *addr, unsigned int region) { int offset; char freeze_br[12]; + struct fdt_resource r; + int ret; snprintf(freeze_br, sizeof(freeze_br), "freeze_br%d", region); @@ -49,13 +51,15 @@ static int intel_get_freeze_br_addr(fdt_addr_t *addr, unsigned int region) return -ENODEV; } - *addr = fdtdec_get_addr(gd->fdt_blob, offset, "reg"); - if (*addr == FDT_ADDR_T_NONE) { + ret = fdt_get_resource(gd->fdt_blob, offset, "reg", 0, &r); + if (ret) { printf("%s has no 'reg' property!\n", freeze_br); - return -ENXIO; + return ret; } - return 0; + *addr = r.start; + + return ret; } static int intel_freeze_br_do_freeze(unsigned int region) From patchwork Mon Nov 7 13:33:50 2022 Content-Type: text/plain; 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07 Nov 2022 05:34:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10523"; a="725138775" X-IronPort-AV: E=Sophos;i="5.96,145,1665471600"; d="scan'208";a="725138775" Received: from pglmail07.png.intel.com ([10.221.193.207]) by FMSMGA003.fm.intel.com with ESMTP; 07 Nov 2022 05:34:20 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id 35B7F4838; Mon, 7 Nov 2022 21:34:20 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 34A6CE00214; Mon, 7 Nov 2022 21:34:20 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , "Chew, Chiau Ee" , Chew@ecsmtp.png.intel.com Subject: [PATCH 2/3] Set/clear reset_req bit before/after PR Date: Mon, 7 Nov 2022 21:33:50 +0800 Message-Id: <20221107133351.26311-2-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20221107133351.26311-1-jit.loon.lim@intel.com> References: <20221107133351.26311-1-jit.loon.lim@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: "Chew, Chiau Ee" HSD #1508949110: For Agilex and Stratix10, before FPGA Partial Reconfiguration (PR) operation, SW need to set reset_req bit in freeze_csr_ctrl register to reset PR region. The same bit need to be cleared after FPGA PR operation is done. Signed-off-by: Chew, Chiau Ee Signed-off-by: Jit Loon Lim --- drivers/fpga/intel_pr.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/intel_pr.c b/drivers/fpga/intel_pr.c index 6637425452..a0a758488b 100644 --- a/drivers/fpga/intel_pr.c +++ b/drivers/fpga/intel_pr.c @@ -81,10 +81,17 @@ static int intel_freeze_br_do_freeze(unsigned int region) writel(FREEZE_CSR_CTRL_FREEZE_REQ, addr + FREEZE_CSR_CTRL_OFFSET); - return wait_for_bit_le32((const u32 *)(addr + + ret = wait_for_bit_le32((const u32 *)(addr + FREEZE_CSR_STATUS_OFFSET), FREEZE_CSR_STATUS_FREEZE_REQ_DONE, true, FREEZE_TIMEOUT, false); + + if (ret) + writel(0, addr + FREEZE_CSR_CTRL_OFFSET); + else + writel(FREEZE_CSR_CTRL_RESET_REQ, addr + FREEZE_CSR_CTRL_OFFSET); + + return ret; } static int intel_freeze_br_do_unfreeze(unsigned int region) @@ -97,6 +104,8 @@ static int intel_freeze_br_do_unfreeze(unsigned int region) if (ret) return ret; + writel(0, addr + FREEZE_CSR_CTRL_OFFSET); + status = readl(addr + FREEZE_CSR_STATUS_OFFSET); if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE) @@ -106,10 +115,14 @@ static int intel_freeze_br_do_unfreeze(unsigned int region) writel(FREEZE_CSR_CTRL_UNFREEZE_REQ, addr + FREEZE_CSR_CTRL_OFFSET); - return wait_for_bit_le32((const u32 *)(addr + + ret = wait_for_bit_le32((const u32 *)(addr + FREEZE_CSR_STATUS_OFFSET), FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE, true, FREEZE_TIMEOUT, false); + + writel(0, addr + FREEZE_CSR_CTRL_OFFSET); + + return ret; } static int do_pr(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) From patchwork Mon Nov 7 13:33:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jit Loon Lim X-Patchwork-Id: 1700649 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; 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Mon, 7 Nov 2022 21:34:24 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id BFE9DE00214; Mon, 7 Nov 2022 21:34:24 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Chew@ecsmtp.png.intel.com Subject: [PATCH 3/3] drivers: fpga: intel_pr: enable illegal request detection Date: Mon, 7 Nov 2022 21:33:51 +0800 Message-Id: <20221107133351.26311-3-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20221107133351.26311-1-jit.loon.lim@intel.com> References: <20221107133351.26311-1-jit.loon.lim@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: "Chew, Chiau Ee" This is to enable check on the freeze_illegal_request register whereby high on any bit of this bus indicates a read or write issue by a static region master when an freeze bridge is in the freeze state. In the case if any of the bit is high, write 1 to first clear the bit and then return with error. Signed-off-by: Chew, Chiau Ee Signed-off-by: Jit Loon Lim --- drivers/fpga/intel_pr.c | 54 ++++++++++++++++++++++++++++++++++------- 1 file changed, 45 insertions(+), 9 deletions(-) diff --git a/drivers/fpga/intel_pr.c b/drivers/fpga/intel_pr.c index a0a758488b..e84845c918 100644 --- a/drivers/fpga/intel_pr.c +++ b/drivers/fpga/intel_pr.c @@ -62,6 +62,49 @@ static int intel_get_freeze_br_addr(fdt_addr_t *addr, unsigned int region) return ret; } +static int intel_freeze_br_req_ack(fdt_addr_t addr, u32 req_ack) +{ + u32 status, illegal, ctrl; + int ret = -ETIMEDOUT; + unsigned long start = get_timer(0); + + while (1) { + illegal = readl(addr + FREEZE_CSR_ILLEGAL_REQ_OFFSET); + if (illegal) { + printf("illegal request 0x%08x detected in freeze bridge\n", illegal); + + writel(illegal, addr + FREEZE_CSR_ILLEGAL_REQ_OFFSET); + + illegal = readl(addr + FREEZE_CSR_ILLEGAL_REQ_OFFSET); + if (illegal) + printf("illegal request 0x%08x detected in freeze bridge are not cleared\n", + illegal); + + ret = -EINVAL; + break; + } + + status = readl(addr + FREEZE_CSR_STATUS_OFFSET); + status &= req_ack; + if (status) { + ctrl = readl(addr + FREEZE_CSR_CTRL_OFFSET); + printf("%s request %x acknowledged %x %x\n", + __func__, req_ack, status, ctrl); + + ret = 0; + break; + } + + if (get_timer(start) > FREEZE_TIMEOUT) + break; + + udelay(1); + WATCHDOG_RESET(); + } + + return ret; +} + static int intel_freeze_br_do_freeze(unsigned int region) { u32 status; @@ -81,11 +124,7 @@ static int intel_freeze_br_do_freeze(unsigned int region) writel(FREEZE_CSR_CTRL_FREEZE_REQ, addr + FREEZE_CSR_CTRL_OFFSET); - ret = wait_for_bit_le32((const u32 *)(addr + - FREEZE_CSR_STATUS_OFFSET), - FREEZE_CSR_STATUS_FREEZE_REQ_DONE, true, - FREEZE_TIMEOUT, false); - + ret = intel_freeze_br_req_ack(addr, FREEZE_CSR_STATUS_FREEZE_REQ_DONE); if (ret) writel(0, addr + FREEZE_CSR_CTRL_OFFSET); else @@ -115,10 +154,7 @@ static int intel_freeze_br_do_unfreeze(unsigned int region) writel(FREEZE_CSR_CTRL_UNFREEZE_REQ, addr + FREEZE_CSR_CTRL_OFFSET); - ret = wait_for_bit_le32((const u32 *)(addr + - FREEZE_CSR_STATUS_OFFSET), - FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE, true, - FREEZE_TIMEOUT, false); + ret = intel_freeze_br_req_ack(addr, FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE); writel(0, addr + FREEZE_CSR_CTRL_OFFSET);