From patchwork Sat Nov 5 18:59:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1700125 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=s31663417 header.b=J3PoKDvh; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N4RdC4chLz23lT for ; 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Sun, 6 Nov 2022 05:59:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1667674760; bh=p9YDZV3SVh65N5p5g+sDDmYbRp27o4nub0l5+Ua3VKI=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=J3PoKDvhApuEyAoHR4cjNCvmbpvk2J/OZ40T+2RY1HFR429dXWIEeyNkwPA7EK9tp mHU1yaiirfCRgKcCOZWd9VPPFo5Xcot1DA7vG7NJ3ISPpmksfeMUA4tBQmsie+MGkk Lc/KX+d9f2EvBnqHiDKyacD4JjvHjf+om+tB8sHQCOLgjibvnDjo24iAQTgKmoJdx/ vm2lFk8Wx+d0+D8s7bEfZa9l9t8rFmWKzL35jOOTXLd89PMCb36IJdOUBjv+LVBISV xQXAhYJJTI3xeLrCQKju0d+a+VtIxCimbzhcElA3qDTOtuKnap5NDn7bqFV1FJgK61 lWYQ86eYKEn7Q== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([87.78.44.193]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MdvmY-1pOnvi0Akw-00b1X1; Sat, 05 Nov 2022 19:59:20 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-spi@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH 1/8] pinctrl: nuvoton: wpcm450: Refactor MFSEL setting code Date: Sat, 5 Nov 2022 19:59:04 +0100 Message-Id: <20221105185911.1547847-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221105185911.1547847-1-j.neuschaefer@gmx.net> References: <20221105185911.1547847-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:O8qPZWuqzhHITt3VaDtMUqy6A+mhRlAcyIBz33LYKVUSnA0k061 eiFGOgB4CIqGiB4MazQ7WXcCbS1g20BwUtujxoGnrLpKrecE+6hwRCpKQxXXuhRCCp3sOYY nqIdtLBweaYTKm6UE9Jf9NoSM+QGGXPgF5vmgLLQ+ZuzzQLEAORevw6Xn4ObjtbY0lErAJ3 kPuVjeMlnaVb3lso+lFaw== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:/kSkirQ6yIk=;ZbO3NPnwS5AqaGY/XtD5IpIPc0R tsuV8YWbMT4oFeb12DQe+y8AEpJqAGYPMHZNzCxovoY+9lPOV4geaYtEaarPft+Rpn4h73Kt1 4Ii3uESLo/r6W3EB9eQZNYFmFH3ASH/wW4a1g7i3/1aUrJLHnOXA9jCgzixyL1k2maPOTuApy d5WH3XI+wV+a18ZDvcGVqEBZdobunWXOS3hbxC3cAhHFwDgMRaOTwDvnMfDu8tfC88T1uQOPW u1uNFbUfMvNWWIam+MMaDk+0D9rNuGkNba/AloMkcsGrV+YP9xTkV6pf8do61VeqFiN/VQCTj QXNO0naRHjUJ/e7zPbww4iPsAxdjckURvF0adISGLt5x4x9p3KUhO3VKv6FiidNMve1PCaCB7 RLRJtTRIjEDqVHPxXJ2ipN77mT/aYWfWgBO84sGVNzqr8OcA5KIfxS7rBJufgfbTY/EFJ5ARq Y7gH/0XoAK4kDrvQUCVV53n6U3ImswM8bZs0fm9EjNI9I4cSE4ag9heIXa9pHxVdwTecCyh6t 2XKDkLhtBqTLNas0jmYBC3ZHZSzPoypOsaEETecyUDLliHJS3zmUkIJhqbEkXl7Msb1GjliWy mPqM+Iy/RAKkAZPruz/oLXa6OHvDRaTQwlqLm6QzQHTSkTGRRTsewwhjjokjQqSz5upr1xxRL tpdXcUY8akmfmCNAn+7GVVeopF91ZupfWX7M7hz5fbAzKU5jK64+lbgwnm4fD3jaFeE4KHeic O+t7FeRscFNtsZWnqnr3PwQiwgUFm+0bc1rMUs9y7PwdMcU8sy97p1T3spZ9s7r1Tskg2L8pF vEabcZjtF8HBfeA8DAOw4ALOsKh+BzagWb/OBx5byi+WFMMO9WdsJXTVn+7cHocetKPsHRNDB BjuqsQ5P66YBH8ntab0bZpGl0kyfTcAYo+Mkuq6MLt5dxw+LuwcFTOPda42/Pacr1WdZMr/Z0 fJI7DRAxgxV779NC7sMwEnCl+5A= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Linus Walleij , Lee Jones , =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Mark Brown , Krzysztof Kozlowski Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" In preparation for the next patch, which makes the logic around setting/resetting bits in MFSEL a little more complicated, move that code to a new function Signed-off-by: Jonathan Neuschäfer --- drivers/pinctrl/nuvoton/pinctrl-wpcm450.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) -- 2.35.1 diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c index 211ad32cc0d8f..49b2177af17b2 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c +++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c @@ -800,6 +800,14 @@ static const struct pinctrl_pin_desc wpcm450_pins[] = { WPCM450_PIN(124), WPCM450_PIN(125), WPCM450_PIN(126), WPCM450_PIN(127), }; +/* Helper function to update MFSEL field according to the selected function */ +static void wpcm450_update_mfsel(struct regmap *gcr_regmap, int reg, int bit, int fn, int fn_selected) +{ + bool value = (fn == fn_selected); + + regmap_update_bits(gcr_regmap, reg, BIT(bit), value ? BIT(bit) : 0); +} + /* Enable mode in pin group */ static void wpcm450_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, int npins, int func) @@ -811,13 +819,11 @@ static void wpcm450_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, cfg = &pincfg[pin[i]]; if (func == fn_gpio || cfg->fn0 == func || cfg->fn1 == func) { if (cfg->reg0) - regmap_update_bits(gcr_regmap, cfg->reg0, - BIT(cfg->bit0), - (cfg->fn0 == func) ? BIT(cfg->bit0) : 0); + wpcm450_update_mfsel(gcr_regmap, cfg->reg0, + cfg->bit0, cfg->fn0, func); if (cfg->reg1) - regmap_update_bits(gcr_regmap, cfg->reg1, - BIT(cfg->bit1), - (cfg->fn1 == func) ? BIT(cfg->bit1) : 0); + wpcm450_update_mfsel(gcr_regmap, cfg->reg1, + cfg->bit1, cfg->fn1, func); } } } From patchwork Sat Nov 5 18:59:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1700128 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=s31663417 header.b=SlDnVSwI; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N4RhH4wgPz23ls for ; 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Sun, 6 Nov 2022 05:59:34 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1667674761; bh=Qpw8OKKBbZVVfzRq9A/GSiYS3wmIwpXxBurfIN6x05I=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=SlDnVSwIFHrbJ4TPSLdlFuzAXHC+bhydtVpb9WMVZB0v6f01S4F78lyUg/+J+C6Tt CMQ8PLC1PWyN6BpBAtQjO0NmP4h4SvP7s7uDegygqsYg0BguryUfEytGL4RH0zMfht 65Rkb8r0evwqpBLKV6LSQhqNBb/ybRZS4oJLDrWdR9Dj2BeeSbS2rOMBzZSxsw4Mz6 kdl9PMtD7MK6sdgM0iIoilyTg/2XyGMx/nZDziyeKE+j2Y5n7Lh7JZu0ona21wuYkS XKvb3IEJwPLoeaIQYNe8pvDquFEfcBna05w9Bbz+8md0+p7JgQRxuXMWjaiRCuCOgy JIPDD+uQ3LSfQ== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([87.78.44.193]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1N1fmq-1p2ITJ2h5M-011x00; Sat, 05 Nov 2022 19:59:21 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-spi@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH 2/8] pinctrl: nuvoton: wpcm450: Fix handling of inverted MFSEL bits Date: Sat, 5 Nov 2022 19:59:05 +0100 Message-Id: <20221105185911.1547847-3-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221105185911.1547847-1-j.neuschaefer@gmx.net> References: <20221105185911.1547847-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:Vfta1KKuPXfyTJlokrlUIHqVt+wLZz8l/XAP30d+cEfJqL6A2LA g5LjfJosVcXeoCtrvPlJNvI6ZX5ynJxH721gUnKyGVOj9SLpUA29/I2PBZtdDVOB+d6EqT2 Dh6Q2yAtBCAYQK1V7mhtYOqApao/igkZ0ZQvTwRlIP8pwqLrQKJpVLYaZ/fzXTl17AwqWjx bR+w2fkM/sYjgaVQBMYHw== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:n3cR5LUqolI=;cP+fOJOaOTtw9hjNLch1t/06EwK N+vvEtSrqWPHeYoWb6HLd+ym+5ej+kC0F1ErWt8n+MfZU3Xs8uP1kuhkMllSbQyTmEXLC7WIL SFdwcTVxNV4oAbP9q/GUqnedEiLtEpH+rTsm9XYG+9QMkLt6GjXh/4k0dHvgxI8XqIDwRaaUM Nln9YkmS4awqNp4Eq5ZKIQSh5nwLWf/q5ecC+rIe6S9ztCMUuZOJxTtWUj2ZKBf8GwfL5W3rd Ni5Vu5vU3NbID+p83WYl/HT2tYHQhu5Ktsmuw8nIuF2YLq9sGt9yqy1NL+V+jwxFnemoqnKm0 tAM+Sp6GXELpvq/Gw8azuUNZhkvg6wd9Ow2sMkIX4M5ovoSX4zMUb6Xa4knAr4qNAIX6NTmk8 gO7Hls5ZE8hvkxmOXdOX/bblzEv/Ln81ClPvOr9g7XGegpVSAFy6ucYqbXE2wndzbSxYfZIRU iZyh0l+K4yJdFAGlkUHaVi7+5oIBCp2TSOzG08oFVQkVRzLW45RhSniQ+8fRIrQ/nGsiwI7T4 wE3IHqoC5kIQiEkMqEWLk2vgiG+xFAzv1jnMB10JKkMuJ2YcDjTiYf8kEmMxonkv1Vb+JMYa9 GoNSL/aFidXyb3dyw53BmX0FhY+WbwUMrOxXMAzA11SND6QaJWQx6OwaYmOElCdhCyTagHj8C rIsNmb3ssRcgmZJSyIWh8w+i8VyIIXB2E2tLNAsHoPphMs6sMe+XfvspRfaFqZz64AKeaTNle JCBj9KboCuv6gq80WVNRc3jTLDOfKf+Mstx1KF+j7UgcJ8SE2hXf4SlBWg8VVURz3w7QC5zmo 6A2Bqn3ZNXPPoeqyoA5LSd8YotnUU9ixrjdHXejGoqEDV6alcWbB2WxXWaix2f5ByAfGHZbKN QyYUnlB2DqFsQXiMNJlF8tvNV1iQ326GUUEZWlGfbu4GW8DVU9WRdf4c+LBbFBhJE7mZvZBR5 wD5J/CG787cp2GsgKDZbeo7U+UQ= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Linus Walleij , Lee Jones , =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Mark Brown , Krzysztof Kozlowski Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" SCS3SEL and KBCCSEL use inverted logic: Whereas in other fields 0 selects the GPIO function and 1 selects the special function, in these two fields, 0 selects the special function and 1 selects the GPIO function. Adjust the code to handle this quirk. Signed-off-by: Jonathan Neuschäfer --- drivers/pinctrl/nuvoton/pinctrl-wpcm450.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) -- 2.35.1 diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c index 49b2177af17b2..2d1c1652cfd9d 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c +++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c @@ -628,6 +628,9 @@ struct wpcm450_pincfg { int fn1, reg1, bit1; }; +/* Add this value to bit0 or bit1 to indicate that the MFSEL bit is inverted */ +#define INV BIT(5) + static const struct wpcm450_pincfg pincfg[] = { /* PIN FUNCTION 1 FUNCTION 2 */ WPCM450_PINCFG(0, none, NONE, 0, none, NONE, 0), @@ -665,7 +668,7 @@ static const struct wpcm450_pincfg pincfg[] = { WPCM450_PINCFG(32, scs1, MFSEL1, 3, none, NONE, 0), WPCM450_PINCFG(33, scs2, MFSEL1, 4, none, NONE, 0), - WPCM450_PINCFG(34, scs3, MFSEL1, 5, none, NONE, 0), + WPCM450_PINCFG(34, scs3, MFSEL1, 5 | INV, none, NONE, 0), WPCM450_PINCFG(35, xcs1, MFSEL1, 29, none, NONE, 0), WPCM450_PINCFG(36, xcs2, MFSEL1, 28, none, NONE, 0), WPCM450_PINCFG(37, none, NONE, 0, none, NONE, 0), /* DVO */ @@ -725,8 +728,8 @@ static const struct wpcm450_pincfg pincfg[] = { WPCM450_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0), WPCM450_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0), WPCM450_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0), - WPCM450_PINCFG(93, kbcc, MFSEL1, 17, none, NONE, 0), - WPCM450_PINCFG(94, kbcc, MFSEL1, 17, none, NONE, 0), + WPCM450_PINCFG(93, kbcc, MFSEL1, 17 | INV, none, NONE, 0), + WPCM450_PINCFG(94, kbcc, MFSEL1, 17 | INV, none, NONE, 0), WPCM450_PINCFG(95, none, NONE, 0, none, NONE, 0), WPCM450_PINCFG(96, none, NONE, 0, none, NONE, 0), @@ -805,6 +808,11 @@ static void wpcm450_update_mfsel(struct regmap *gcr_regmap, int reg, int bit, in { bool value = (fn == fn_selected); + if (bit & INV) { + value = !value; + bit &= ~INV; + } + regmap_update_bits(gcr_regmap, reg, BIT(bit), value ? BIT(bit) : 0); } From patchwork Sat Nov 5 18:59:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1700129 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=s31663417 header.b=Z9sT2LWs; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N4RjK6T9Kz23ls for ; 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Sun, 6 Nov 2022 05:59:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1667674763; bh=0zlGVmWFUJWAxvnZusk8TMaPc0CG35sV5kM6R3yKrvQ=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=Z9sT2LWsbOVZ0gISJr2OamL1OHDHt0LHMzUhGvXkZ7CIJwhcuCk4Vqx3sNrCvOEIF BjGRMCAY8ekPr4mpqE8oAaiyvMzcjX4Mjcw4IAFOwWOQDgFsC3uNiKVZ+fSzTn2ViP jlxKdbGWYCOXh7js05ZRiCq1FxcpAX+4Vvp6HVCfSzBLezO4oja2kRfRBRF0cixx1j eFVpR9VntQoCRXdEemXJgKUUy+Y9/3SvozOQQNRqRFUuHFNCdiqRM53d1KYQXUBmpC RdJ/Yw9d9+m6Hq70OaCd8Z/ws3mvp0Pl8yeCWW604NHcQJbJ652irDKk7uvL2olSS5 xxewg8QnXXotw== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([87.78.44.193]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1M3DNt-1osmUp3DC9-003cZd; Sat, 05 Nov 2022 19:59:22 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-spi@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH 3/8] dt-bindings: spi: Add Nuvoton WPCM450 Flash Interface Unit (FIU) Date: Sat, 5 Nov 2022 19:59:06 +0100 Message-Id: <20221105185911.1547847-4-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221105185911.1547847-1-j.neuschaefer@gmx.net> References: <20221105185911.1547847-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:4mhJHiA7uzMLYJ28yXXBf74eXRxCJyYO5pHRgHTydKeBdEX8Xng jKj6nr7av4t9KvdfbSaYqoC3m8aehbRPG7urF+6tCT5rfmaaWOdhonv92WnicRVsm/GbOLf 7itL2tJ/L/HFZJjH9ah3OR0WI+V4DNBD/FbE7pEwRgZ4mfbf1X88XnS6xrwVUTnrrbgqtcS Qgyh3Tesm9geoyrBpkP9Q== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:MmDo+WVVpq4=;yqWimBjtK0/euTlSj8+VYUx4t1y AjazQdJ3cov+i4w0b9Gg+zq589JFK2Bj0jg61kS7n4VXyzrvO0Na/Q366ZYVTclXXldEtFfmm 1YBa3b14OMfyL/GDQfCTZwckWFclfhTqOLXfmjuVhM/+OJanN0JiEQITYiN7XGX1Uwdv0L637 jAN81dS6UPmo7h6uwZpxsmlpVjbJ9nOVGN1/MpAmDFCn7abEYEcWNRUzEp+bWauk2/P2qWGun WGnYAVl6wGLLjT34DfP6eNfvyFIUAZPC+4wL2VHjV8EHg6j2HIgyHIxBbrQrpTmg4jsrbKAzV oLjx8lEZ5MBRHyojqoDLF6F7iEOHG2KX75EUBYUm6PVHvvRz0P1oWhPeVaUoH8btnkPLOjEyW GHXLIhKqxaghjaFdLkIzQbBQCsA3me8wjFFB36k/YOkQBegkkYxtOGwiyX1P4VTxM25F3XeeZ HY65++p2HYQICeB1VlbLSKcDOHad+3CzkzJwuAII8s0VCUvAnD2Nxhm2qaj7V95zJ2S4ixz0E HOtQwyOJgCcEOp0IGMcqOMcOi5oODq8tVNWEtN69HQl9Us81kK7F45DKt+EGlgdJU+vf3QJ5B nuczmjLXWS8bLne8x2EJMs0ajDMokB/evw5ZiNN0kEs2af5dKokEaLP/GsVgAgHykJQlNXGh1 03mWs8vUqxGuNQBOK6vn1ubFj+pEtFz9X53Y+1Ik2HmbkJCqxug/qQZwdauzlq2nIartKE5v0 mJgg9DUODgbAdJ6jQVPk2XQ2ktpEWZ3o8yzb3PExP3JCdNyl1stsNVDDu79rUYMgGvaTzM5TA t12QYCheXgpRmi61yk6g+MovRsxKQHVrII+56O7u7WFLFvELClRmfsFiKYpXkOaGKJpaE80tq s0b1hk1ZQmGMRBoT9XV2ouCbZBjZtNu+M5VK8wExT0P9td+glPjyV+zaKWug9AL6Cgh3A7ENz +WdSZg== X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Linus Walleij , Lee Jones , =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Mark Brown , Krzysztof Kozlowski Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" The Flash Interface Unit (FIU) is the SPI flash controller in the Nuvoton WPCM450 BMC SoC. It supports four chip selects, and direct (memory-mapped) access to 16 MiB per chip. Larger flash chips can be accessed by software-defined SPI transfers. The FIU in newer NPCM7xx SoCs is not compatible with the WPCM450 FIU. Signed-off-by: Jonathan Neuschäfer --- .../bindings/spi/nuvoton,wpcm450-fiu.yaml | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml -- 2.35.1 diff --git a/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml b/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml new file mode 100644 index 0000000000000..dc0ea2184f8d0 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/nuvoton,wpcm450-fiu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 Flash Interface Unit (FIU) + +maintainers: + - Jonathan Neuschäfer + +allOf: + - $ref: "/schemas/spi/spi-controller.yaml#" + +properties: + compatible: + const: nuvoton,wpcm450-fiu + + reg: + items: + - description: FIU registers + - description: Memory-mapped flash contents + + reg-names: + items: + - const: control + - const: memory + minItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + nuvoton,shm: + $ref: /schemas/types.yaml#/definitions/phandle + description: a phandle to the SHM block (see ../arm/nuvoton,shm.yaml) + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + spi@c8000000 { + compatible = "nuvoton,wpcm450-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>; + reg-names = "control", "memory"; + clocks = <&clk WPCM450_CLK_FIU>; + nuvoton,shm = <&shm>; + + flash@0 { + compatible = "jedec,spi-nor"; + }; + }; + + shm: syscon@c8001000 { + compatible = "nuvoton,wpcm450-shm", "syscon"; + reg = <0xc8001000 0x1000>; + }; + + - | + #include + spi@c8000000 { + compatible = "nuvoton,wpcm450-fiu"; + // the "memory" resource may be omitted + reg = <0xc8000000 0x1000>; + reg-names = "control"; + }; From patchwork Sat Nov 5 18:59:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1700126 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; 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b=DH9p80zOnQO7O2133KFhyH6bATFm/mowoCqO+1si3qQ2Ozf/OKu6yTILTGVEp/ErZ wgR6jLXvRdi+tBEnOS/L8W8WrYJxNEP+vY7gO/TMVCBmfMl7MlHCG2KCDIxu65Fzia IomHOQywxG4ksExKigd+xbM6NWq4L7EerAWJwM2dmDkwtrRH6s7nel/mFWfuZN+F0J BgTiBC3EiQH6ZKGaKulz4N4LFDU9L6sV+fhkfazK0g4gkjJ6OTqRvSKnCf5LlfnqfH ZDsbEhUTrw+2ReooXZVFB1kv7HbwYHFVTAknfajI539DMk/mUlSMN/1TBACVwIrQil KwNqEMTnyfyKQ== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([87.78.44.193]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MysRk-1pCkjG0qzy-00vwp3; Sat, 05 Nov 2022 19:59:24 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-spi@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH 4/8] dt-bindings: mfd: syscon: Add nuvoton,wpcm450-shm Date: Sat, 5 Nov 2022 19:59:07 +0100 Message-Id: <20221105185911.1547847-5-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221105185911.1547847-1-j.neuschaefer@gmx.net> References: <20221105185911.1547847-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:XooQiqVVZh/n9MhWx2shMMIRTpxqDE+qHgQ0zij3Pxan6E+iOFd onv+cowItr0XS/P5Dt/9XOhHTSwGBwUUgVDxC0NXg+PbKfKDjXtojVIiQZaiDrDcFubJetD D47zRFWoS+AeOTxi++yGMkrdTJ8w034AGU+nBpacci70jWcKuWoDumY8mNkW3SBJcw67J0b tBzqNGFDTCnS3xdpIRgWQ== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:SAMvsW5d1p0=;YDbGzosJ1GuA93A0FnmAXh011rQ fKekKhUXNqbp5PMBw6bGKZ65UAKEdOy+Do3OCMie+L9Pu5cy2uPSod+Bp0/tZBYiLMyTmKVet 8CPcwW0aw/aZkP3AL/0QD/n5z6pwrfENwnszFpGMZ6XJWn3+2Q9z5r7mw2rz2WnaWSjhTIzk+ V2zA33ULmW474odP/+S3uhJOmoscHdgRaiqE/aRan1Yfd/bYmQl1BQYr+g3m4LxVpnD941hno jkndRaSVSZHDA1wuXdCIYcR+t3nwKLAgE0PFGT7dSHgyRwt+na7peQIkD0GqMGHz6q1BL2mZW qpDTxkBE5shMCSRiI62/Gk1soATJbhWQlJ11uBz3lsv69XS6jlLXVBOTke7EHeaXeRDxG/MzM BN4Fhxq9Aqd1WCmWmlCcjxNt17bIvuOddZZO1HEWzHdmxnF9SEwA+UPISNWISyAh9OLnN75lq f+lg2BEe/Jpatnb5iwodTb0pGz+K9QjpepHmj3fNQXIKNNeQ2Ef44djwveWjIxeq7Xa9gkoaU +R3uiukppWxiH07P4BOM+7quDfWs0b4R9v/jF544IpS2pawc2qbqUaAox83jqszDCLepnB7oT yk8XabJ4uIKWIiQTBgS+qUozJrN+orhz+ei508zkxUdypu2kpfoGYXJqPwqLMB5YlNQ8IsyUE B6nbHHfh3IsFI2wUOxAcYROuisjyPnwTxr1EFQoeVNZOFI16fUT2Bmw6btcqzPXIiQ5yZOvPR eMOlXJiEJDoE1elwPkM8AF0Y4W8bCZYQGmtV8nlZIpZYfJhqCxRDNUZE0O0FzPSAiowz6AtIH 77t7v/YLfzFz5sUxBYHvVwwVSxaKrVHfhxBcso34ggfW8KHrrQaTxuGTUpnUFuWVcfDWA5mFi 3Tj8O6h0M1TuD3148R8t4UzTmYxVtnSWFZPio2sgIL/F9nu+LYB70BrqnzGnfKVnKMR5o9/bC rHQyvQKItWKcRfQQvQABLiVLcI4= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Linus Walleij , Lee Jones , =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Mark Brown , Krzysztof Kozlowski Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" The Shared Memory interface (SHM) is a piece of hardware in Nuvoton BMCs that allows a host processor (connected via LPC) to access flash and RAM that belong to the BMC. The SHM includes a register block accessible from the BMC side. Signed-off-by: Jonathan Neuschäfer --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.35.1 diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 4e4baf53796de..1b01bd0104316 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -53,6 +53,7 @@ properties: - microchip,lan966x-cpu-syscon - microchip,sparx5-cpu-syscon - mstar,msc313-pmsleep + - nuvoton,wpcm450-shm - rockchip,px30-qos - rockchip,rk3036-qos - rockchip,rk3066-qos From patchwork Sat Nov 5 18:59:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1700131 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; 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b=Ukqrb2I4cNKZhLTaa0ZHbYr1o3BP0sP7HsJy53KHHe23tW60EztLdqwc1kLuGGNz6 LNmPU+gDxWqnn0qx6SQduszrDao4U9bW46nNWoVYM3HZIfWAeC3ggoO/Lq4XBtFbqm Zb6y2Je8pnjDAt/0zE7f8PWOtV8Pngwe/+7qoiUC62QezjxVwoB7zTCHNJoS1mggA3 nXhA3zHKf4/h7asSjls2CnIu1ziNr2F1XEqAM1yOJ3ssTsgMdiSkILQm5tyIU99jfF JcAZ+ZwfVYxji3q8iRdYbUOa4owcHC+Dzp5ZmtltxyLDn1iAQCb0wg9SzXZVCmUkoR yfMJS8+2UT6AA== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([87.78.44.193]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1McH5a-1pRZ563gnU-00ck71; Sat, 05 Nov 2022 19:59:24 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-spi@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH 5/8] ARM: dts: wpcm450: Add FIU SPI controller node Date: Sat, 5 Nov 2022 19:59:08 +0100 Message-Id: <20221105185911.1547847-6-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221105185911.1547847-1-j.neuschaefer@gmx.net> References: <20221105185911.1547847-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:CRar9ivUzCsj49qmjSPQqicgToyrxgj4f3IEg3FyzRlYqRIlXZc QE5AaQx6SFWqlBCzK7A0KBDJ30lM8CbktVojH8nGNDcdJfmS6rhZH7j12pUg1+51Bt5FFih AjK2gVZf3bNcwypSPW42cjgG2y8ijYg4r2oF/veWkdBY2fp4pU9xS/Lirk4Cy/vc013eCiU NelRJOl++C9eX4U1HdNYw== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:f8EehY0JCzw=;S7sM7wxvJNtt9sMfxlbJ8MIhnBr NGIBM5nXSeHgU+AKI4nURc1AXiBsVn9B4v/ss85+/5qG2IPQQ6vvHXYGFjUedCqR4sNqznOfD MdvO1PVYTs7VzPun0g7vPTb8WNONuVRD6u/XDlkNkReYrCU8BWqKSRPmldVHYIYjweCiJQa4B CKosZeYnyJYyZzqLJLQZbR1e3KPgvlPt5dfzVkg2yPSUTUl8kinEtLymrqq3PVIVq6m49A0iw kW2VkW3xi05qaH15sqelp3jC2VMS+Dm5vFAzsqJKnAI5d/PdPKoguDK/rkEq7MTyemrY7oxfR hDXCrOvLqn520qHuSG44jlmNOtwcQe+8LwB5eXdlWlCLiwUQ7LAWdcjv5hCP1dbLsjGuCV05x SuxJjak9JKnAhQoD4ouNlzgOmdzcu82vUpMe5SWaOjgbIRJt86amZQFcp4t6BLvyronbfP8Z+ gn7H3MHVhtGL+W7feonATIvAhnyIgU9HlNQDRWSA9ON5haKP0HurSsKRZS9sy+nDtFRuvO7Qm XWl93jzhzF4uTspuG4s0Q5mfDNbBjg1DnaieJzm/hDHeehJ+GCcP1VRQOHNSDQYF/IQ6MS9ay E1IbMiqIgOLAhgbFlvIZ0y78GdqIUWPTDpfI6xJCy/mgQNn+/GiGHB1n8dua3PTa5Y1KsgndW xDCqzCAsGt0eJwRGN7nOe2Vf0w4I3soxJSG1peQzwGiWZG/dgiLED7OE3wxVEH1+ZRN14DPU6 y/qeXDwh7UJ+iy7H5glm9iCKP7usQrw/P2588O9kGrBjcKc0i7Q0YqBiIl45Rp8cVxzVm0LxG jLd6ZuP8I815OyYNlkizaRieTzVujxi80Io8fXdozUw1CBOWLqh4nPI548TuWmM9Qdb/4BaJR 6uzKRiKdEVBQEXkm5nYfU4M4H5St8kc5aCqFSzH5C0JdFNK7DOgL9Z/e0RRaEvIpUx6s+B917 tm3mSbG9dGXS30EQYt/yFVm/fXk= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Linus Walleij , Lee Jones , =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Mark Brown , Krzysztof Kozlowski Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Add the SPI controller (FIU, Flash Interface Unit) to the WPCM450 devicetree, according to the newly defined binding, as well as the SHM (shared memory interface) syscon. Signed-off-by: Jonathan Neuschäfer --- This patch depends on the series: [PATCH v5 0/6] Nuvoton WPCM450 clock and reset driver --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.35.1 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index 439f9047ad651..299fcbba3089b 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -470,5 +470,21 @@ hg7_pins: mux-hg7 { function = "hg7"; }; }; + + fiu: spi-controller@c8000000 { + compatible = "nuvoton,wpcm450-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>; + reg-names = "control", "memory"; + clocks = <&clk WPCM450_CLK_FIU>; + status = "disabled"; + }; + + shm: syscon@c8001000 { + compatible = "nuvoton,wpcm450-shm", "syscon"; + reg = <0xc8001000 0x1000>; + reg-io-width = <1>; + }; }; }; From patchwork Sat Nov 5 18:59:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1700130 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=s31663417 header.b=gy03nHyE; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N4RkM5jkWz23ls for ; Sun, 6 Nov 2022 06:04:27 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4N4RkM4YXnz3cNg for ; Sun, 6 Nov 2022 06:04:27 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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t=1667674766; bh=bK1RUXAe+xpxxpGUjTTgd1x6zwE6ztff1lqUp39rxNQ=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=gy03nHyEDASlmMOM28yBL3RQ4FCZJnUx4G1ivYXgWT0gF+FylMDp8YzFzeWUUYCr2 p3mlP+9WXVAvGUy0QQtc4rtgm5FbBFLLzRLmkVoO1h0yAiTmosw3hGQHfhmr6yjMRr FkpxXNbXj7QYj89/ZsDIp/aQM51btLzTrgxI645ZzaAFM9u5gslUIrd2bj+X1Z3wrX CjhC6r1l5QrNRHd7OgMRVOXwDM45iAA5QGNTCaVrg1snGTJmADjGnbW/EBF0EUXuHu dvTrSE1Uvwzr1l+usJbgsUYd2gR/cM7xQYZjRZ7Qcmj/pTb06avNokiYjpNusRTuRc z6dIa0G9efSVg== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([87.78.44.193]) by mail.gmx.net (mrgmx005 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MF3He-1op9LK1TeS-00FPgw; Sat, 05 Nov 2022 19:59:26 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-spi@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH 6/8] ARM: dts: wpcm450-supermicro-x9sci-ln4f: Add SPI flash Date: Sat, 5 Nov 2022 19:59:09 +0100 Message-Id: <20221105185911.1547847-7-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221105185911.1547847-1-j.neuschaefer@gmx.net> References: <20221105185911.1547847-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:FZU0RXgcUNGQI/fiMCkh0UXPBADSKhLECE8zLUwxtzD6QQYaUX1 qF/e4enn/IXaBQeQO766lveS0QEfFavPwpY03jbtfdeGVozY/ciEUkF/B5I46RfSJMeey1S dEg9k2/zA+OClMPTfA1RzImkg5Y3FqJnQabRCOiFSsZF/KQMLwixLJi09R60XlszJkZO8vY 3pPld68pPgH5l/Vxfi4vA== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:2VwYnSXCeMo=;7BAaka/fpvRGgAWjY1Gv6Aadw4m kkbfhU43cVx9601VeNjAMuIINK1PSYnH/36qg6AbeRm6NYuZW5+u5XR6yqf3KurydPTDGQ4E0 TVoqpC03N1SEPLZbpITQIpT5y1lj7hmaQofwUlsb8VRXjn2hxQFJ0mB4agnXiU5TMBy56D7+G hNpgkyAb5TTJpuZ9CQ/boVyPYP1f6Bj81ACoPizhHdFfnKgb+kJV6QVRWaSElpSjLsQPUUVnP t0DqojkAW1/b/d7Z//onZwYAhu9DTAU5oG5wc1AcNLJuv0DU/O8aExcuC/LdrehkkDy37sVY6 sMajYmW8cPcO8M3gDUW4YKu3tjVo1A1y37jluVIzvsmSfnkMWwDL0vB2Vsa+hLnbi1dik5feR DTnTYAZCh4XYun1ChTrio7Evg1xSX5sOz4cRwwXq4axZQ0/4Qaz2nBoJHHqPm3DsXrqZWUaoE DErpINkUvuC03XHPkQ1FLY/cZIHMkrk02eiT9JjFQ89EV5cLaAv4TLgIuJif+qf6xX0Ik+WRc NuoMih3e+mw8sceweC5BOWnQa3oa6GvoLwyR7VqK6VtAObQ5rfRdyP4ApF6Xa2ZZITQFR1aGz FN6+SyhNHSHTscHz7L22BZw0cEVXpPzQiQ9th8/0vhANOX+ScIu+20QLSB4Q1IZgKhYoU/pri COXHOlbs3MnJPixQU+WitLrt5DLl0Wq8E/u5wqTO5xDCzsXSUbt5zaT/G/R2qTmvmFDFusNuh EW2mPDe+XE3lIHTr4N/ipd5bjYQJO6IdDNEN3DejyH0IZ+YbiW8dquS+yyRA7mgt9jrNery0C t9V2L2NIhLuVza7woT6xlzYNqeJCALPOcZtbDSwkPBHkihbXOTgDLU+khXIlSkhcSJlMCFYDu LjnPM0DSu9DwQO/msUgODx0xK+dhUFoWQ8rwO5k/vKlhpDuAJZpcKP0he2mgvyZZ/0y5wMIgQ LAArtPgvZh+6qxOfdTteSJugGV0= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Linus Walleij , Lee Jones , =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Mark Brown , Krzysztof Kozlowski Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Add the BMC firmware flash to the devicetree, so that it can be accessed from Linux. Signed-off-by: Jonathan Neuschäfer --- .../boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.35.1 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts index d4472ffdac928..b78c116cbc18e 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts +++ b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts @@ -58,6 +58,15 @@ heartbeat { }; }; +&fiu { + status = "okay"; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + }; +}; + &gpio0 { gpio-line-names = /* 0 */ "", "host-reset-control-n", "", "", "", "", "", "", From patchwork Sat Nov 5 18:59:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1700132 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1667674767; bh=NM6v0lFGiR0uEkPynnfwY/N9MRh4qhtWVnH0D2SCNeg=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=pqQQgU7t5kRDr9kn8GgUH7w/R2Kx6qqCRn8V0XZ1eyaZIwZ2DJB6fcKxbU6Mxu1or zxZ5IuFcwdpFrFgGDTTEYTjbMx8yWKb9yWMl9DZkypn3JC24b+mJUZVPUn8lC5AILE qV3jxGojV16B+fZN964QLk5mBFBdzq31Whnhqc808K/AzvJpKCBrdOrcZGvqJ9xfFe kLvdUzaafGNlIcTC0hJW+46f9UJmgDuIZWMd+yHP3S6EJUu83TaYCdNePuXAn/fwcU akJDTo1etoRFSl3CVQeUbporNCVufhJsv6fmn2wasjMY57CK9AUjlTJE6TO7/lWJWq jpKDNhjVbH7CA== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([87.78.44.193]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MNt0C-1ogSBD2h7A-00OEmi; Sat, 05 Nov 2022 19:59:27 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-spi@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH 7/8] spi: wpcm-fiu: Add driver for Nuvoton WPCM450 Flash Interface Unit (FIU) Date: Sat, 5 Nov 2022 19:59:10 +0100 Message-Id: <20221105185911.1547847-8-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221105185911.1547847-1-j.neuschaefer@gmx.net> References: <20221105185911.1547847-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:2KODUNLOlhqbVz3eBGVCkVWFgSpdQODBtrQ+lKHWzlgI0FhJsGO o8/SMS99+uIjqF/X3qgreoF303PC4DT0NSPXlHYKZwlWUp5h6noxv5wZA8GulNFBuSFyRdv gUNyQzeYWmghog+hltJ29QFjViov732g5WQzwobs1+DGqjpGMAqlO2tbBeyu3mo2+u09oR4 3U3xeCDDaacMhMYdD0hGg== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:OYaYFq+SuKU=;rW1RETpz4b8K6GoBjHyPuk47tvS 2XtHZDOpIsBNzXfDd8Q3eNyJV55t0ljrDfZYPpK1snmnsPtuLAwTBeVEwcyPCmoKrO+BUYOa+ FV3eJ1c2sp4s9c30BGaUALgq1OY9Ta1fh3Pu3Du6FzunLUwVpf0wP4BcqQ+/Hu6T7btBUsuTu 2Hm36kpJJXw+Ku3XuqIYi06fwXaLh+yt56J32BdS3WbTf9KuexxX9K0A4tAH2TKqPGRW0OeWK tNpuu2yx/eW0rlkvn3RpdAu+ZbKTPlh9sJd+pZqDTverCbw33jGs7AHIoD1uVdjD1r9yt7Gyl TcYBs2MldYt/JoWLvTIEC7mMStqMAyUkV7vRVFjaVvCiy0nc8bJFsGGem7X3bwDfB3tekOa+E jlGDnOM1jltDGhGun8eUoQ9J7eTln6zUyBHvZdRt+nkqhfm0a4pAPQj1UNeS9JuozCVZ3aaBv 4KiXz/2PxY/ohaxK96gqCq5x3iVFZjqEqKAygAfnAzXFqkjqq0nF/X/Fpe2GAhPKuVCOKxnPY g5oBcxZk6o4aKWQlAhAcNHSQhTaJZcM9lEDm8I3HoIPTPtrg+WBVh3PKlzlLCEixGmYEK1wua jHsttNPSsM8q3fZxi1SXYuBP6Q1QGx1taLH8W7fbIMvV7BKSAoGYNSQwFesdmK8lUvIwJIt2Y SKjPi1ALMDVPkp72Xmz3nb3v4R+/gDrZq/iUESOrN4unxZpCT/RXvpPHjiJWQXNUHWkqqoLT2 5ebyrNrE+2Y2UicvLTceB18sqvR94Khp9I+sWIv/NBU5mllvM68QvLiThrNhFAoZpqm6SeCN1 /aOE2qyB1D131OOVDjkpH4V7LPN2D/iwKkCRPpu/y0YjIviwXWbFTh4/pMBr2wfssYa+81geu C143KLXvH9TETePIm7fxuF+nf37Bw3lFL0M4Y/QicWbqrgcYHn9kFKQjc7KT5S8Bp92e4qe+4 WBpWAd/h99bLzz1XOs4B21KlnGw= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Linus Walleij , Lee Jones , =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Mark Brown , Krzysztof Kozlowski Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" The Flash Interface Unit (FIU) is the SPI flash controller in the Nuvoton WPCM450 BMC SoC. It supports four chip selects, and direct (memory-mapped) access to 16 MiB per chip. Larger flash chips can be accessed by software-defined SPI transfers. The FIU in newer NPCM7xx SoCs is not compatible with the WPCM450 FIU. Signed-off-by: Jonathan Neuschäfer --- drivers/spi/Kconfig | 11 + drivers/spi/Makefile | 1 + drivers/spi/spi-wpcm-fiu.c | 443 +++++++++++++++++++++++++++++++++++++ 3 files changed, 455 insertions(+) create mode 100644 drivers/spi/spi-wpcm-fiu.c -- 2.35.1 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d1bb62f7368b7..ee5f9e61cc280 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -635,6 +635,17 @@ config SPI_MTK_SNFI is implemented as a SPI-MEM controller with pipelined ECC capcability. +config SPI_WPCM_FIU + tristate "Nuvoton WPCM450 Flash Interface Unit" + depends on ARCH_NPCM || COMPILE_TEST + select REGMAP + help + This enables support got the Flash Interface Unit SPI controller + present in the Nuvoton WPCM450 SoC. + + This driver does not support generic SPI. The implementation only + supports the spi-mem interface. + config SPI_NPCM_FIU tristate "Nuvoton NPCM FLASH Interface Unit" depends on ARCH_NPCM || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 4b34e855c8412..e30196d0a4cf9 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -83,6 +83,7 @@ obj-$(CONFIG_SPI_MTK_NOR) += spi-mtk-nor.o obj-$(CONFIG_SPI_MTK_SNFI) += spi-mtk-snfi.o obj-$(CONFIG_SPI_MXIC) += spi-mxic.o obj-$(CONFIG_SPI_MXS) += spi-mxs.o +obj-$(CONFIG_SPI_WPCM_FIU) += spi-wpcm-fiu.o obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o obj-$(CONFIG_SPI_NPCM_PSPI) += spi-npcm-pspi.o obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o diff --git a/drivers/spi/spi-wpcm-fiu.c b/drivers/spi/spi-wpcm-fiu.c new file mode 100644 index 0000000000000..d68693d4cd8bd --- /dev/null +++ b/drivers/spi/spi-wpcm-fiu.c @@ -0,0 +1,443 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2022 Jonathan Neuschäfer + +#include +#include +#include +#include +#include +#include +#include +#include + +#define FIU_CFG 0x00 +#define FIU_BURST_BFG 0x01 +#define FIU_RESP_CFG 0x02 +#define FIU_CFBB_PROT 0x03 +#define FIU_FWIN1_LOW 0x04 +#define FIU_FWIN1_HIGH 0x06 +#define FIU_FWIN2_LOW 0x08 +#define FIU_FWIN2_HIGH 0x0a +#define FIU_FWIN3_LOW 0x0c +#define FIU_FWIN3_HIGH 0x0e +#define FIU_PROT_LOCK 0x10 +#define FIU_PROT_CLEAR 0x11 +#define FIU_SPI_FL_CFG 0x14 +#define FIU_UMA_CODE 0x16 +#define FIU_UMA_AB0 0x17 +#define FIU_UMA_AB1 0x18 +#define FIU_UMA_AB2 0x19 +#define FIU_UMA_DB0 0x1a +#define FIU_UMA_DB1 0x1b +#define FIU_UMA_DB2 0x1c +#define FIU_UMA_DB3 0x1d +#define FIU_UMA_CTS 0x1e +#define FIU_UMA_ECTS 0x1f + +#define FIU_BURST_CFG_R16 3 + +#define FIU_UMA_CTS_D_SIZE(x) (x) +#define FIU_UMA_CTS_A_SIZE BIT(3) +#define FIU_UMA_CTS_WR BIT(4) +#define FIU_UMA_CTS_CS(x) ((x) << 5) +#define FIU_UMA_CTS_EXEC_DONE BIT(7) + +#define SHM_FLASH_SIZE 0x02 +#define SHM_FLASH_SIZE_STALL_HOST BIT(6) + +/* + * I observed a typical wait time of 16 iterations for a UMA transfer to + * finish, so this should be a safe limit. + */ +#define UMA_WAIT_ITERATIONS 100 + +struct wpcm_fiu_spi { + struct device *dev; + struct clk *clk; + void __iomem *regs; + struct regmap *shm_regmap; +}; + +static void wpcm_fiu_set_opcode(struct wpcm_fiu_spi *fiu, u8 opcode) +{ + writeb(opcode, fiu->regs + FIU_UMA_CODE); +} + +static void wpcm_fiu_set_addr(struct wpcm_fiu_spi *fiu, u32 addr) +{ + writeb((addr >> 0) & 0xff, fiu->regs + FIU_UMA_AB0); + writeb((addr >> 8) & 0xff, fiu->regs + FIU_UMA_AB1); + writeb((addr >> 16) & 0xff, fiu->regs + FIU_UMA_AB2); +} + +static void wpcm_fiu_set_data(struct wpcm_fiu_spi *fiu, const u8 *data, unsigned int nbytes) +{ + int i; + + for (i = 0; i < nbytes; i++) + writeb(data[i], fiu->regs + FIU_UMA_DB0 + i); +} + +static void wpcm_fiu_get_data(struct wpcm_fiu_spi *fiu, u8 *data, unsigned int nbytes) +{ + int i; + + for (i = 0; i < nbytes; i++) + data[i] = readb(fiu->regs + FIU_UMA_DB0 + i); +} + +/* + * Perform a UMA (User Mode Access) operation, i.e. a software-controlled SPI transfer. + */ +static int wpcm_fiu_do_uma(struct wpcm_fiu_spi *fiu, unsigned int cs, + bool use_addr, bool write, int data_bytes) +{ + int i = 0; + u8 cts = FIU_UMA_CTS_EXEC_DONE | FIU_UMA_CTS_CS(cs); + + if (use_addr) + cts |= FIU_UMA_CTS_A_SIZE; + if (write) + cts |= FIU_UMA_CTS_WR; + cts |= FIU_UMA_CTS_D_SIZE(data_bytes); + + writeb(cts, fiu->regs + FIU_UMA_CTS); + + for (i = 0; i < UMA_WAIT_ITERATIONS; i++) + if (!(readb(fiu->regs + FIU_UMA_CTS) & FIU_UMA_CTS_EXEC_DONE)) + return 0; + + dev_info(fiu->dev, "UMA transfer has not finished in %d iterations\n", UMA_WAIT_ITERATIONS); + return -EIO; +} + +static void wpcm_fiu_ects_assert(struct wpcm_fiu_spi *fiu, unsigned int cs) +{ + u8 ects = readb(fiu->regs + FIU_UMA_ECTS); + + ects &= ~BIT(cs); + writeb(ects, fiu->regs + FIU_UMA_ECTS); +} + +static void wpcm_fiu_ects_deassert(struct wpcm_fiu_spi *fiu, unsigned int cs) +{ + u8 ects = readb(fiu->regs + FIU_UMA_ECTS); + + ects |= BIT(cs); + writeb(ects, fiu->regs + FIU_UMA_ECTS); +} + +struct wpcm_fiu_op_shape { + bool (*match)(const struct spi_mem_op *op); + int (*exec)(struct spi_mem *mem, const struct spi_mem_op *op); +}; + +static bool wpcm_fiu_normal_match(const struct spi_mem_op *op) +{ + // Opcode 0x0b (FAST READ) is treated differently in hardware + if (op->cmd.opcode == 0x0b) + return false; + + return (op->addr.nbytes == 0 || op->addr.nbytes == 3) && + op->dummy.nbytes == 0 && op->data.nbytes <= 4; +} + +static int wpcm_fiu_normal_exec(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); + int ret; + + wpcm_fiu_set_opcode(fiu, op->cmd.opcode); + wpcm_fiu_set_addr(fiu, op->addr.val); + if (op->data.dir == SPI_MEM_DATA_OUT) + wpcm_fiu_set_data(fiu, op->data.buf.out, op->data.nbytes); + + ret = wpcm_fiu_do_uma(fiu, mem->spi->chip_select, op->addr.nbytes == 3, + op->data.dir == SPI_MEM_DATA_OUT, op->data.nbytes); + + if (op->data.dir == SPI_MEM_DATA_IN) + wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes); + + return ret; +} + +static bool wpcm_fiu_fast_read_match(const struct spi_mem_op *op) +{ + return op->cmd.opcode == 0x0b && op->addr.nbytes == 3 && + op->dummy.nbytes == 1 && + op->data.nbytes >= 1 && op->data.nbytes <= 4 && + op->data.dir == SPI_MEM_DATA_IN; +} + +static int wpcm_fiu_fast_read_exec(struct spi_mem *mem, const struct spi_mem_op *op) +{ + return -EINVAL; +} + +/* + * 4-byte addressing. + * + * Flash view: [ C A A A A D D D D] + * bytes: 13 aa bb cc dd -> 5a a5 f0 0f + * FIU's view: [ C A A A][ C D D D D] + * FIU mode: [ read/write][ read ] + */ +static bool wpcm_fiu_4ba_match(const struct spi_mem_op *op) +{ + return op->addr.nbytes == 4 && op->dummy.nbytes == 0 && op->data.nbytes <= 4; +} + +static int wpcm_fiu_4ba_exec(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); + int cs = mem->spi->chip_select; + + wpcm_fiu_ects_assert(fiu, cs); + + wpcm_fiu_set_opcode(fiu, op->cmd.opcode); + wpcm_fiu_set_addr(fiu, op->addr.val >> 8); + wpcm_fiu_do_uma(fiu, cs, true, false, 0); + + wpcm_fiu_set_opcode(fiu, op->addr.val & 0xff); + wpcm_fiu_set_addr(fiu, 0); + if (op->data.dir == SPI_MEM_DATA_OUT) + wpcm_fiu_set_data(fiu, op->data.buf.out, op->data.nbytes); + wpcm_fiu_do_uma(fiu, cs, false, op->data.dir == SPI_MEM_DATA_OUT, op->data.nbytes); + + wpcm_fiu_ects_deassert(fiu, cs); + + if (op->data.dir == SPI_MEM_DATA_IN) + wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes); + + return 0; +} + +/* + * RDID (Read Identification) needs special handling because Linux expects to + * be able to read 6 ID bytes and FIU can only read up to 4 at once. + * + * We're lucky in this case, because executing the RDID instruction twice will + * result in the same result. + * + * What we do is as follows (C: write command/opcode byte, D: read data byte, + * A: write address byte): + * + * 1. C D D D + * 2. C A A A D D D + */ +static bool wpcm_fiu_rdid_match(const struct spi_mem_op *op) +{ + return op->cmd.opcode == 0x9f && op->addr.nbytes == 0 && + op->dummy.nbytes == 0 && op->data.nbytes == 6 && + op->data.dir == SPI_MEM_DATA_IN; +} + +static int wpcm_fiu_rdid_exec(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); + int cs = mem->spi->chip_select; + + /* First transfer */ + wpcm_fiu_set_opcode(fiu, op->cmd.opcode); + wpcm_fiu_set_addr(fiu, 0); + wpcm_fiu_do_uma(fiu, cs, false, false, 3); + wpcm_fiu_get_data(fiu, op->data.buf.in, 3); + + /* Second transfer */ + wpcm_fiu_set_opcode(fiu, op->cmd.opcode); + wpcm_fiu_set_addr(fiu, 0); + wpcm_fiu_do_uma(fiu, cs, true, false, 3); + wpcm_fiu_get_data(fiu, op->data.buf.in + 3, 3); + + return 0; +} + +/* + * With some dummy bytes. + * + * C A A A X* X D D D D + * [C A A A D*][C D D D D] + */ +static bool wpcm_fiu_dummy_match(const struct spi_mem_op *op) +{ + // Opcode 0x0b (FAST READ) is treated differently in hardware + if (op->cmd.opcode == 0x0b) + return false; + + return (op->addr.nbytes == 0 || op->addr.nbytes == 3) && + op->dummy.nbytes >= 1 && op->dummy.nbytes <= 5 && + op->data.nbytes <= 4; +} + +static int wpcm_fiu_dummy_exec(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); + int cs = mem->spi->chip_select; + + wpcm_fiu_ects_assert(fiu, cs); + + /* First transfer */ + wpcm_fiu_set_opcode(fiu, op->cmd.opcode); + wpcm_fiu_set_addr(fiu, op->addr.val); + wpcm_fiu_do_uma(fiu, cs, op->addr.nbytes != 0, true, op->dummy.nbytes - 1); + + /* Second transfer */ + wpcm_fiu_set_opcode(fiu, 0); + wpcm_fiu_set_addr(fiu, 0); + wpcm_fiu_do_uma(fiu, cs, false, false, op->data.nbytes); + wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes); + + wpcm_fiu_ects_deassert(fiu, cs); + + return 0; +} + +static const struct wpcm_fiu_op_shape wpcm_fiu_op_shapes[] = { + { wpcm_fiu_normal_match, wpcm_fiu_normal_exec }, + { wpcm_fiu_fast_read_match, wpcm_fiu_fast_read_exec }, + { wpcm_fiu_4ba_match, wpcm_fiu_4ba_exec }, + { wpcm_fiu_rdid_match, wpcm_fiu_rdid_exec }, + { wpcm_fiu_dummy_match, wpcm_fiu_dummy_exec }, +}; + +static const struct wpcm_fiu_op_shape *wpcm_fiu_find_op_shape(const struct spi_mem_op *op) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(wpcm_fiu_op_shapes); i++) { + const struct wpcm_fiu_op_shape *shape = &wpcm_fiu_op_shapes[i]; + + if (shape->match(op)) + return shape; + } + + return NULL; +} + +static bool wpcm_fiu_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) +{ + if (!spi_mem_default_supports_op(mem, op)) + return false; + + if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) + return false; + + if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 || + op->dummy.buswidth > 1 || op->data.buswidth > 1) + return false; + + return wpcm_fiu_find_op_shape(op) != NULL; +} + +/* + * In order to ensure the integrity of SPI transfers performed via UMA, + * temporarily disable (stall) memory accesses coming from the host CPU. + */ +static void wpcm_fiu_stall_host(struct wpcm_fiu_spi *fiu, bool stall) +{ + if (fiu->shm_regmap) { + int res = regmap_update_bits(fiu->shm_regmap, SHM_FLASH_SIZE, + SHM_FLASH_SIZE_STALL_HOST, + stall ? SHM_FLASH_SIZE_STALL_HOST : 0); + if (res) + dev_warn(fiu->dev, "Failed to (un)stall host memory accesses: %d\n", res); + } +} + +static int wpcm_fiu_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller); + const struct wpcm_fiu_op_shape *shape = wpcm_fiu_find_op_shape(op); + + wpcm_fiu_stall_host(fiu, true); + + if (shape) + return shape->exec(mem, op); + + wpcm_fiu_stall_host(fiu, false); + + return -ENOTSUPP; +} + +static int wpcm_fiu_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) +{ + if (op->data.nbytes > 4) + op->data.nbytes = 4; + + return 0; +} + +static const struct spi_controller_mem_ops wpcm_fiu_mem_ops = { + .adjust_op_size = wpcm_fiu_adjust_op_size, + .supports_op = wpcm_fiu_supports_op, + .exec_op = wpcm_fiu_exec_op, +}; + +static void wpcm_fiu_hw_init(struct wpcm_fiu_spi *fiu) +{ + /* Deassert all manually asserted chip selects */ + writeb(0x0f, fiu->regs + FIU_UMA_ECTS); +} + +static int wpcm_fiu_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct spi_controller *ctrl; + struct wpcm_fiu_spi *fiu; + struct resource *res; + + ctrl = devm_spi_alloc_master(dev, sizeof(*fiu)); + if (!ctrl) + return -ENOMEM; + + fiu = spi_controller_get_devdata(ctrl); + fiu->dev = dev; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control"); + fiu->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(fiu->regs)) { + dev_err(dev, "Failed to map registers\n"); + return PTR_ERR(fiu->regs); + } + + fiu->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(fiu->clk)) + return PTR_ERR(fiu->clk); + + fiu->shm_regmap = syscon_regmap_lookup_by_phandle_optional(dev->of_node, "nuvoton,shm"); + + wpcm_fiu_hw_init(fiu); + + ctrl->bus_num = -1; + ctrl->mem_ops = &wpcm_fiu_mem_ops; + ctrl->num_chipselect = 4; + ctrl->dev.of_node = dev->of_node; + + /* + * The FIU doesn't include a clock divider, the clock is entirely + * determined by the AHB3 bus clock. + */ + ctrl->min_speed_hz = ctrl->max_speed_hz = clk_get_rate(fiu->clk); + + return devm_spi_register_controller(dev, ctrl); +} + +static const struct of_device_id wpcm_fiu_dt_ids[] = { + { .compatible = "nuvoton,wpcm450-fiu", }, + { } +}; +MODULE_DEVICE_TABLE(of, wpcm_fiu_dt_ids); + +static struct platform_driver wpcm_fiu_driver = { + .driver = { + .name = "wpcm450-fiu", + .bus = &platform_bus_type, + .of_match_table = wpcm_fiu_dt_ids, + }, + .probe = wpcm_fiu_probe, +}; +module_platform_driver(wpcm_fiu_driver); + +MODULE_DESCRIPTION("Nuvoton WPCM450 FIU SPI controller driver"); +MODULE_AUTHOR("Jonathan Neuschäfer "); +MODULE_LICENSE("GPL"); From patchwork Sat Nov 5 18:59:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1700133 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; 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b=R/FiV9Fg+SF9iBOFI1rcYT+poYx0llGUbBL2CU9PGJJ2IS4XLlGfI176v2lmd3Fl3 fXgqT1BXgP+HHQBUPrzdlcVYhQhLf4aRohbQ5ZVv36qlLCs5jQbYLEYt/u+PJpfhIM 544S4L3ZiOBLw11J7uwGE8Q5Mw9KtQvdR7u43qUDlnHccwfnMD31/Jk8i9AzclXFrg XrpGjKaNAwXA40Fq7yfqmBQDfFrG5kUlCys84tGJXU/5OBySSF5DAmnk2OEvDAyqsV jc5xQWFvH1uADn3QVB+VaLj6Ad69lExtdTYmikNBafsFVVbwxWTvmtegUvywymT5BY /EXF28mSUX3iw== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([87.78.44.193]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MXp5Q-1oWWYm1aay-00YChF; Sat, 05 Nov 2022 19:59:28 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-spi@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH 8/8] spi: wpcm-fiu: Add direct map support Date: Sat, 5 Nov 2022 19:59:11 +0100 Message-Id: <20221105185911.1547847-9-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221105185911.1547847-1-j.neuschaefer@gmx.net> References: <20221105185911.1547847-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:9V2ZEZNXbUL5fJgOg60HwNFPLB73gmrjIGRAPTVp/sNNac9zK1d 5UDoJcPw0nIsuE7FZ8KCLcHIfz58KPYWQvdhIo8CIU/EzQuxHAHm+XT2KOdPqzrHG1NszEP m1ME/7xu25bTayYm4BJIW2aSreCn6fKWoCcFtacYiyGy+EEVfWp+0eTv4LcQu/mEKyDffyp 2r6iyMuxikbYLE3S4jMYA== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:u4ojvdMZIts=;SlqvjLzK+y0Xc6K4ER98wtDp10q uHKtssdXHpWlIjADhYxl7EznuhbAE0IeW47bH3v502JnVxiGOYKlF1k8nWGKHJIT9rSqPgoyv YQNR3TGd5isFq3YCnnaqIdnBUQb/mQbqZS0nsdFcMkMMfBxwVrbNoXskbqN5605fPchKeUwX7 HxzzHcw//qyIdaCiTm4bB7osiSTF6rHA79YkHOX3L8r2htuL3RKDqxdyBMd2i7Xdrc4S/IZOH w8YWuc31nPkTQO4c2MLbrV00sfHXngzpBl7Bx/rZRQ4q5DJe4ZCogq56OL6TX7VtEiPJr5lmB qDLTaChbf8sMbaazK85199TXdUXuU1f7iobeBBWx/vsU14P9GTiLwmQ60Os2DybFD1kPa7jSy DyRGwOa4Jsc/coJzO5iqag6B6AQDp3PYb04GUDGHabGe34/MRXXAAM7Wse+x6kZf6BOss2chf ykHyVMxO4LJBYoAIBn2ooprsIHvjp+bkNc7MITPoOwk4DJ8lXOPPdNy44W5lblyAnzVYQv95h 4wzkhtvF1TToO6ij03q1T0UaKGvFCKSuadlZr8sSHizQzkm7k5Y5vqggMe27i4WHpJUYPldSb aMtySlOpQ2zjJBCKeUlIp/o7T8uzhfNA709QT4CLGAz0Xf8gp47RJWYPzEDYkQnWusvLTt4k7 nHMyaq2sl8ki3tTV1k+3Cxczu/3GdvDp/Btogtfv2CpL2J04y22EIJV3MTuGOhggW+sJcPm68 oVDTyBrhogKfmLzGBFsIdg82v9BP/mxACzcmGRAYWgYVuCKo8Eg+jfuy6pBZpqSGALUWZngKi kYHquwOhZBRzc9o6miGRwOGAuPlpyq7cAMZP99hqUYzdAKFUj5jsKscPtPGfCXTRAJ6r6dOU2 YN22BSncJRv9qmxSqYSgfhG6HEm0CpNhwBOwZViAT09ZTftJlgVuuzYBJREQ5i9Ap/5yeQrGY BCP2Mv7zoYoR+qrlQQhx2c59Y2Q= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Linus Walleij , Lee Jones , =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Mark Brown , Krzysztof Kozlowski Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Besides software controlled SPI transfers (UMA, "user mode access"), FIU also supports a 16 MiB mapping window per attached flash chip. This patch implements direct mapped read access, to speed up flash reads. Without direct mapping: # time dd if=/dev/mtd0ro of=dump bs=1M 16+0 records in 16+0 records out real 1m 47.74s user 0m 0.00s sys 1m 47.75s With direct mapping: # time dd if=/dev/mtd0ro of=dump bs=1M 16+0 records in 16+0 records out real 0m 30.81s user 0m 0.00s sys 0m 30.81s Signed-off-by: Jonathan Neuschäfer --- drivers/spi/spi-wpcm-fiu.c | 64 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) -- 2.35.1 diff --git a/drivers/spi/spi-wpcm-fiu.c b/drivers/spi/spi-wpcm-fiu.c index d68693d4cd8bd..eda46c766ad9d 100644 --- a/drivers/spi/spi-wpcm-fiu.c +++ b/drivers/spi/spi-wpcm-fiu.c @@ -51,10 +51,16 @@ */ #define UMA_WAIT_ITERATIONS 100 +/* The memory-mapped view of flash is 16 MiB long */ +#define MAX_MEMORY_SIZE_PER_CS (16 << 20) +#define MAX_MEMORY_SIZE_TOTAL (4 * MAX_MEMORY_SIZE_PER_CS) + struct wpcm_fiu_spi { struct device *dev; struct clk *clk; void __iomem *regs; + void __iomem *memory; + size_t memory_size; struct regmap *shm_regmap; }; @@ -367,14 +373,64 @@ static int wpcm_fiu_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) return 0; } +static int wpcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc) +{ + struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller); + int cs = desc->mem->spi->chip_select; + + if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN) + return -ENOTSUPP; + + /* + * Unfortunately, FIU only supports a 16 MiB direct mapping window (per + * attached flash chip), but the SPI MEM core doesn't support partial + * direct mappings. This means that we can't support direct mapping on + * flashes that are bigger than 16 MiB. + */ + if (desc->info.offset + desc->info.length > MAX_MEMORY_SIZE_PER_CS) + return -ENOTSUPP; + + /* Don't read past the memory window */ + if (cs * MAX_MEMORY_SIZE_PER_CS + desc->info.offset + desc->info.length > fiu->memory_size) + return -ENOTSUPP; + + return 0; +} + +static int wpcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, void *buf) +{ + struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller); + int cs = desc->mem->spi->chip_select; + + if (offs >= MAX_MEMORY_SIZE_PER_CS) + return -ENOTSUPP; + + offs += cs * MAX_MEMORY_SIZE_PER_CS; + + if (!fiu->memory || offs >= fiu->memory_size) + return -ENOTSUPP; + + len = min_t(size_t, len, fiu->memory_size - offs); + memcpy_fromio(buf, fiu->memory + offs, len); + + return len; +} + static const struct spi_controller_mem_ops wpcm_fiu_mem_ops = { .adjust_op_size = wpcm_fiu_adjust_op_size, .supports_op = wpcm_fiu_supports_op, .exec_op = wpcm_fiu_exec_op, + .dirmap_create = wpcm_fiu_dirmap_create, + .dirmap_read = wpcm_fiu_direct_read, }; static void wpcm_fiu_hw_init(struct wpcm_fiu_spi *fiu) { + /* Configure memory-mapped flash access */ + writeb(FIU_BURST_CFG_R16, fiu->regs + FIU_BURST_BFG); + writeb(MAX_MEMORY_SIZE_TOTAL / (512 << 10), fiu->regs + FIU_CFG); + writeb(MAX_MEMORY_SIZE_PER_CS / (512 << 10) | BIT(6), fiu->regs + FIU_SPI_FL_CFG); + /* Deassert all manually asserted chip selects */ writeb(0x0f, fiu->regs + FIU_UMA_ECTS); } @@ -404,6 +460,14 @@ static int wpcm_fiu_probe(struct platform_device *pdev) if (IS_ERR(fiu->clk)) return PTR_ERR(fiu->clk); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory"); + fiu->memory = devm_ioremap_resource(dev, res); + fiu->memory_size = min_t(size_t, resource_size(res), MAX_MEMORY_SIZE_TOTAL); + if (IS_ERR(fiu->regs)) { + dev_err(dev, "Failed to map flash memory window\n"); + return PTR_ERR(fiu->memory); + } + fiu->shm_regmap = syscon_regmap_lookup_by_phandle_optional(dev->of_node, "nuvoton,shm"); wpcm_fiu_hw_init(fiu);