From patchwork Fri Nov 4 16:18:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1699736 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=s31663417 header.b=QctwYSyn; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N3mCN2zFjz23lQ for ; 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In the WPCM450 SoC, each timer runs off a clock can be gated individually. To model this correctly, the timer node in the devicetree needs to take multiple clock inputs. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Rob Herring --- v4-5: - no changes v3: - Add R-b tag v2: - no changes --- .../devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.35.1 diff --git a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml index 737af78ad70c3..d53e1bb98b8a6 100644 --- a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml +++ b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml @@ -25,7 +25,13 @@ properties: - description: The timer interrupt of timer 0 clocks: - maxItems: 1 + items: + - description: The reference clock for timer 0 + - description: The reference clock for timer 1 + - description: The reference clock for timer 2 + - description: The reference clock for timer 3 + - description: The reference clock for timer 4 + minItems: 1 required: - compatible From patchwork Fri Nov 4 16:18:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1699731 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=s31663417 header.b=LeN39DnS; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N3m7F3Xm4z23ls for ; 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Sat, 5 Nov 2022 03:19:42 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1667578744; bh=tqgQ7pawhIV4t9HvNdKf2jVTg7Dq96Y1ZvNJLJ1+csY=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=LeN39DnSIJFltd1q0GRj0/rLFNblWaRZrO5sUWBuw0Uuq2vZ1WXmaer2vkUaVO78S Bp3DFTH1UHAMYM819LJEnzeY1SwNue5QXNVnBDHVQ3x0hAhzze13SBr4knJcEAFYTK JiDHcmcR1Qbb/HbmsjMbWrGlRuuS4wLCOfArD6PcMzBI/cmrwmLkP6Imznr7PkV1I8 g6PRp/3kMEjJ0/0n6kB9r8HM2ruMMqWvxYqPwRruENG070LPeBG1YRubmaXBpvnuyw KIYbqzJBgmOEbzS+5mPKcmzV/TteZGn+liRwJ/Gpi5iZ4QMi/m3I5uwEkHEWztfHZe OWmHLN5gxlOQQ== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([95.223.44.31]) by mail.gmx.net (mrgmx005 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MyKHm-1pEGyy0Xkq-00ykiN; Fri, 04 Nov 2022 17:19:04 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH v5 2/6] clocksource: timer-npcm7xx: Enable timer 1 clock before use Date: Fri, 4 Nov 2022 17:18:46 +0100 Message-Id: <20221104161850.2889894-3-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104161850.2889894-1-j.neuschaefer@gmx.net> References: <20221104161850.2889894-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:AcLaAkbCO8V1wMAgSOaX3/AGdk7f/JhdypdOHpr/VMjkCavhWCj DA4QJ2+U9R4Vmq4sT5ZO5NL6Yk+NdzVX5DxYzvz3qw6sM2FsvSjhicOQzbIOkEdAzO45wpo bFMS6RMVfGSQSZLnUwxFGwGtpvBoMy12/GR2GJ7XuEsQclttCEj/xNyZSxyPHpb+KFC6a3L EKkDwSoBcLubHKN+ZDsoA== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:NVVijpYq+Pk=;5OKIg1RcUiXCS6JevaCWZe+ZBEB XMH8/xamCxMyuihH3uIjXBCZIbC7gZntVPSHTooLhp/B1oS2cc91Hxz6jcwf9kZWpkHo+Qube CW8hpFyTz6TZr7ABc6Orq1uSriIXt1cX88NvwASgasOIy5bfAA+jG2T3PtAay20SGDHVTG32e tB8XfVU6MW41rORmsUJ7XNfo0rZv8vX/RQ4opsiRILAvbxdLTe1kMhIeMhD5fyyneKcs/mK94 1cM/NYe6LvX4WRvV1eAj6lrCGABdExxsFr88pnSsjJ882ooUXld15kpa2PwxSVGkS4wqOvtiG vQFTWGnLSuhUSbdvgJbBdhl699Sfb4bw7P8rVBCf4+LW/xlf1S9EZd30CNiMdd1aIE4Ty7avS HXUUgfy2O/2ayCZbYwhAHUNwGY2VKLaOHvS1h42cu2q5HwKStNWDjhIyxEHN/lee3WJenwBzr ARDACNLRfVpWXlvCJoqOO19vczgrXOaxOjXBB+4B/sXJJn97n1YBZ4NSfeztjEwDx+msIQ2jF vJ6I3j5S8IgESY4vmPlm5RJbb75cX9cTM6ufdMLCvwqf5vipC0zk/lRG/XY08Mq3cq7aVbs9U AoxYOvwhAv9KWd3tFWPxIs0OiOGi6+OxgDEc9ph1wesRTPkY0ZMqrH9wdW4eliwPl+Ju1w4X6 n5pSPHc28WfdE4hRDzUkFhWHdzqK0EFO4PYEKRS5Hri5PG90a9i8vdWdOKP/AiQJ8AoNjNsi+ JDL2k+6c64DOXWuQySRO4b9vej+SgZBsgzw+8BKRoemn9s2euovELFJhxxAZwVfg+5+vqw9dt egFBAaaec0cl3vqOYXIyuRYpMnsBYi6REoiwHi1yt8d2UDAFiyld9z+kL5wPo4KKBcqFN83gq XyS5VUoAZ+gsshDDl8ZSVJ+MXb7uSHbFm9CC2m2oq3/90PPb7sN02Jl0OvjiymjwaF/QjILXP pNJItw== X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" In the WPCM450 SoC, the clocks for each timer can be gated individually. To prevent the timer 1 clock from being gated, enable it explicitly. Signed-off-by: Jonathan Neuschäfer --- Daniel Lezcano mentioned that he applied this patch, but I wasn't able to find it in linux-next, so I'm sending it again. v5: - no changes relative to v3 v4: - not included v3: - no changes v2: - Provide context in pr_warn message v1: - https://lore.kernel.org/lkml/20220422183012.444674-3-j.neuschaefer@gmx.net/ --- drivers/clocksource/timer-npcm7xx.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.35.1 diff --git a/drivers/clocksource/timer-npcm7xx.c b/drivers/clocksource/timer-npcm7xx.c index a00520cbb660a..9af30af5f989a 100644 --- a/drivers/clocksource/timer-npcm7xx.c +++ b/drivers/clocksource/timer-npcm7xx.c @@ -188,6 +188,7 @@ static void __init npcm7xx_clocksource_init(void) static int __init npcm7xx_timer_init(struct device_node *np) { + struct clk *clk; int ret; ret = timer_of_init(np, &npcm7xx_to); @@ -199,6 +200,15 @@ static int __init npcm7xx_timer_init(struct device_node *np) npcm7xx_to.of_clk.rate = npcm7xx_to.of_clk.rate / (NPCM7XX_Tx_MIN_PRESCALE + 1); + /* Enable the clock for timer1, if it exists */ + clk = of_clk_get(np, 1); + if (clk) { + if (!IS_ERR(clk)) + clk_prepare_enable(clk); + else + pr_warn("%pOF: Failed to get clock for timer1: %pe", np, clk); + } + npcm7xx_clocksource_init(); npcm7xx_clockevents_init(); From patchwork Fri Nov 4 16:18:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1699737 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=s31663417 header.b=ddRWtqOt; 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Fri, 04 Nov 2022 17:19:07 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH v5 3/6] dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller Date: Fri, 4 Nov 2022 17:18:47 +0100 Message-Id: <20221104161850.2889894-4-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104161850.2889894-1-j.neuschaefer@gmx.net> References: <20221104161850.2889894-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:Q/MRyQzs4UmAld8Aqho5hQzCgQujH0HLFpkNasG2BgxnN/PLjA7 4EM0Ovl4uGOM9MLk4YhIcyfw1+S7s5YyAxsKxQhHCSG0qlLr9vv89exHE6mq24z/8uqM1wS yc8Q9SogcBP882BHhubmb/8NZZig+uT9SBKlWPJ+yqPMzTMTojjhNo4xankKs+ILuBAas0G ftNty+6PgZbodl8F8epHg== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:F05KtP1a8bw=;zprdSDIHjVY9+z5ZfevBy1dfzUI RULmQQaUeJ+JS2rHOAGJXxSRZ+43XUlNX5gN7I++B1hQbHwppQ4TJ2e1Bqe+7zKXI29ngck3M JtwqzuBfAiZh+/OMvMZARhRVOIjWrVnRPgRlwnTDPc230MfLLGgObsH/YJ53Y7DLoKBwE5MA6 oUPo80XViKP3mL6IjsHQxQodQk2U8IpqIbYSaB6ZjhDLKfky7hgm0IDmoS+MJydQJ4OzsZ0xH HffpQKrUDRTWWE7GhcCutEruJg1nA3hioYivWjzjHHtuIuzLl6QjB1Hj7/VNxKhgn1fE19p6D KvFk3bTViCRTCbmZomuw1ol4TFcshWnaMcIUHcFAO4yhB6j0g/OWs96iIYqgaYhseUKolAuca 2rVsZHlJGpe9RlGOuo9pwd2W9ydg+3heZLUkdF/Sbz71lBUZziobxnDjmvINzvPPeXlFkxWmp b67aNiZgEfJu9y7L9cdBZo8ztEtL4fJwk4HG/R/9GWxn8QfhJucGwcNJ1USkCyr+ei15/ef/q vHoxn4u/aeuc3d+Hcftb22iY2ZwsdZzZ8pXQIMAIyLkyr25YESQZ5HE7dYHPHltFq+/P5b2tG wZSds5CPSlA9XDNHYMpjwMb0kL2I1/rNswmrJb7vcLr7izZnJUpEeJi2CpLJiNaBWXaUuShez LtzFzblkd7oebF93Zg9MrbwBnZjc7iTrBaMjcXm1o2Kkofglfs1xzAkVEB/IwLkEEg0SbYH48 RW+PrsRJpPDwBB/WXFI12Mn2L9Wu2k07zUCsMmmRZrnAYlvZrZjFeF9mGsYHCVmYNMBmWRnds fy97RXVMvi+ZO00KKlvVaG2HOQxA2fdpMP9j4v2kAi2rl/b4Tod9CJ7jPjiC4UbQP+Dbdf+pi /eIcQhfqVPgc6x9PF23mHj5a4jnNkF92Jp1RMZcIf9Jj0DNez+oEP7GxUlH5fR6AGONebP8oM c06Q+g== X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Krzysztof Kozlowski , Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Krzysztof Kozlowski , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" The Nuvoton WPCM450 SoC has a combined clock and reset controller. Add a devicetree binding for it, as well as definitions for the bit numbers used by it. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Krzysztof Kozlowski --- v5: - no changes v4: - https://lore.kernel.org/lkml/20220610072141.347795-4-j.neuschaefer@gmx.net/ - Add R-b tag v3: - Change clock-output-names and clock-names from "refclk" to "ref", suggested by Krzysztof Kozlowski v2: - https://lore.kernel.org/lkml/20220429172030.398011-5-j.neuschaefer@gmx.net/ - Various improvements, suggested by Krzysztof Kozlowski v1: - https://lore.kernel.org/lkml/20220422183012.444674-5-j.neuschaefer@gmx.net/ --- .../bindings/clock/nuvoton,wpcm450-clk.yaml | 66 ++++++++++++++++++ .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 +++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h -- 2.35.1 diff --git a/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml new file mode 100644 index 0000000000000..525024a58df4c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,wpcm450-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 clock controller + +maintainers: + - Jonathan Neuschäfer + +description: + The clock controller of the Nuvoton WPCM450 SoC supplies clocks and resets to + the rest of the chip. + +properties: + compatible: + const: nuvoton,wpcm450-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference clock oscillator (should be 48 MHz) + + clock-names: + items: + - const: ref + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + - | + #include + #include + + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-output-names = "ref"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + clk: clock-controller@b0000200 { + reg = <0xb0000200 0x100>; + compatible = "nuvoton,wpcm450-clk"; + clocks = <&refclk>; + clock-names = "ref"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/nuvoton,wpcm450-clk.h b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h new file mode 100644 index 0000000000000..86e1c895921b7 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H +#define _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H + +/* Clocks based on CLKEN bits */ +#define WPCM450_CLK_FIU 0 +#define WPCM450_CLK_XBUS 1 +#define WPCM450_CLK_KCS 2 +#define WPCM450_CLK_SHM 4 +#define WPCM450_CLK_USB1 5 +#define WPCM450_CLK_EMC0 6 +#define WPCM450_CLK_EMC1 7 +#define WPCM450_CLK_USB0 8 +#define WPCM450_CLK_PECI 9 +#define WPCM450_CLK_AES 10 +#define WPCM450_CLK_UART0 11 +#define WPCM450_CLK_UART1 12 +#define WPCM450_CLK_SMB2 13 +#define WPCM450_CLK_SMB3 14 +#define WPCM450_CLK_SMB4 15 +#define WPCM450_CLK_SMB5 16 +#define WPCM450_CLK_HUART 17 +#define WPCM450_CLK_PWM 18 +#define WPCM450_CLK_TIMER0 19 +#define WPCM450_CLK_TIMER1 20 +#define WPCM450_CLK_TIMER2 21 +#define WPCM450_CLK_TIMER3 22 +#define WPCM450_CLK_TIMER4 23 +#define WPCM450_CLK_MFT0 24 +#define WPCM450_CLK_MFT1 25 +#define WPCM450_CLK_WDT 26 +#define WPCM450_CLK_ADC 27 +#define WPCM450_CLK_SDIO 28 +#define WPCM450_CLK_SSPI 29 +#define WPCM450_CLK_SMB0 30 +#define WPCM450_CLK_SMB1 31 + +/* Other clocks */ +#define WPCM450_CLK_USBPHY 32 + +#define WPCM450_NUM_CLKS 33 + +/* Resets based on IPSRST bits */ +#define WPCM450_RESET_FIU 0 +#define WPCM450_RESET_EMC0 6 +#define WPCM450_RESET_EMC1 7 +#define WPCM450_RESET_USB0 8 +#define WPCM450_RESET_USB1 9 +#define WPCM450_RESET_AES_PECI 10 +#define WPCM450_RESET_UART 11 +#define WPCM450_RESET_MC 12 +#define WPCM450_RESET_SMB2 13 +#define WPCM450_RESET_SMB3 14 +#define WPCM450_RESET_SMB4 15 +#define WPCM450_RESET_SMB5 16 +#define WPCM450_RESET_PWM 18 +#define WPCM450_RESET_TIMER 19 +#define WPCM450_RESET_ADC 27 +#define WPCM450_RESET_SDIO 28 +#define WPCM450_RESET_SSPI 29 +#define WPCM450_RESET_SMB0 30 +#define WPCM450_RESET_SMB1 31 + +#define WPCM450_NUM_RESETS 32 + +#endif /* _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H */ From patchwork Fri Nov 4 16:18:48 2022 Content-Type: text/plain; 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Sat, 5 Nov 2022 03:19:43 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1667578748; bh=5nTOWHVLx+MZr7NjLvj6ZC6mnVnRo8KPzHbjhk46sVU=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=pF0UJd52/aoFrY9j6aW5ecjl4zTwGWbLjZdGdE5a2s3toZv4u+cabdtZBkk5O1oDJ fTjBSuliX+AQe0TzgqrBoCCIMTfBXi50hRMgJ9RyyIo+7+po6iuK1ebUkdePSimxEl WrDQB5ROVK3VWHEIN2xpLOK746BkidAW4A0u19Mt9ooBlQnQTBGFrFBPXV3eGoHX3C LO036qKbFjUNYv/R1saX769DfDsgt6QF17QJtW3OeRjx+RoHP/X/c4s9fm25bQEWhM 5VwR373Am3wu21GW/3yPhKlk0FLGekFFUepaVz94peSjPnqNnP3Thk7D8NDz6pFLNI AD3hoS8XL+cPw== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([95.223.44.31]) by mail.gmx.net (mrgmx005 [212.227.17.190]) with ESMTPSA (Nemesis) id 1Mt75H-1pAi5F2ik5-00tXrC; Fri, 04 Nov 2022 17:19:08 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH v5 4/6] ARM: dts: wpcm450: Add clock controller node Date: Fri, 4 Nov 2022 17:18:48 +0100 Message-Id: <20221104161850.2889894-5-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104161850.2889894-1-j.neuschaefer@gmx.net> References: <20221104161850.2889894-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:6GvRklvuiyAtWqrEnqxNuJ2Hc85LbGEBI/GCoPGar4I+bEWfCpu i0tKTbICpY+FZVhd472ngdn11RIAaonUb0UVXfgtUIoWPuuxsPTn8E59MMQWpo+2o/t6dQ2 XTqCnuyfrC2rYN4rlb0YPgzBt8Q1/+IMxuM2Qktm3/3AXPyj9Sxq4nshOqwU4exHo8FigD4 oVALzHtdq9oBvvqyDsCpw== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:3f2zS5TzCt4=;IAeV4M4Oen9SP2XuT03OCcXQkfT EReOc8Rd+WPVqYjTKIzmrx+94zn5TMR407ldOXqk9l4ZwbLyflmVeDq0R+yC/RGTGYjTsc78V EUzbCcDgR8BLLFJN9ivjmvefdxYRv6plJSSWFqLYxOJRovK3SdWYSqAJ+wTo9t54NPSdZ/6or w2T35/DGf7VcU9M445YwXr/+9h6WvKjz2vlTXJpq23yoC2S4CM+oFS0MVfdDa2JbYLkNmw81L FeDupeOwxuGWUKzkB+9+ER2WR7c6WyG7Sjet/PfNOMMUM9t3Uw1m/HyfcsZHZ6IaHtjfcX2Y3 jCm9omGRPoUyCjIBmUEHrtjcssj9fansfrPLFK8NYTbBFnkmu9uB5YRq9vHkB5sH6twX56qro hdbQcyS+EO8h/WdL89foTy+VImi913I8LLeHkot2xipqZ8U5bweH4MwvDInjQNNzcIo1cInwy 3cJRTVS1K9Mzt/h14OnyNJi0S4IgYm64n0+yglOdotM67pnkZLspYJh2lwfKZVjyeCq+mtX+9 xfF/oS0BbOJk2ye/fO7HYlQuUYl+ImEstolMKVxmYRaqoBtvqG40Oqqo4BxoTs5JS5ptjXqRg zetpCutRxARXJ50ohSJL4bQymyo9/X+pepcGfk4oQM2GQfYZK5gbHh5lDQ3zH1WIgYKIZWkQo BmqS7yX8awToAF2usdBXeU72J2N64UX1hyraGq+FI4m730XrkZpEHWj9xcK0qxiVFv9YNk6Tg 21581uGlpdbYqdFbT3uW2EyLpcqe8Y19NZrAa3NnxDvUspj7mCe28m2qZ/YsX1KMeR+RsquKx Dj2KSQZLVPxXa5zfxBRe2O7/LZAbs/NzAkccAuAdpWvJvBnstVouKuWlDt4ZjxEiCXdPl+2AO Z44UsehWDpz4TJB9m66pkMSZZLJgPkpePJwT7tLsXkUUXNveepZqNE4OwQDhHJ24S6v7mwt07 XYHl5SHqlqVEWWrRaVJ+03+VhJ0= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Krzysztof Kozlowski , Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This declares the clock controller and the necessary 48 Mhz reference clock in the WPCM450 device. Switching devices over to the clock controller is intentionally done in a separate patch to give time for the clock controller driver to land. Signed-off-by: Jonathan Neuschäfer --- v4-5: - no changes v3: - Change clock-output-names and clock-names from "refclk" to "ref" v2: - https://lore.kernel.org/lkml/20220429172030.398011-6-j.neuschaefer@gmx.net/ - no changes --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.35.1 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index b9b669cd632f1..332cc222c7dc5 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -37,6 +37,14 @@ clk24m: clock-24mhz { #clock-cells = <0>; }; + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-output-names = "ref"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -49,6 +57,15 @@ gcr: syscon@b0000000 { reg = <0xb0000000 0x200>; }; + clk: clock-controller@b0000200 { + compatible = "nuvoton,wpcm450-clk"; + reg = <0xb0000200 0x100>; + clocks = <&refclk>; + clock-names = "ref"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + serial0: serial@b8000000 { compatible = "nuvoton,wpcm450-uart"; reg = <0xb8000000 0x20>; From patchwork Fri Nov 4 16:18:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1699740 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=s31663417 header.b=C/qYWSoL; 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Fri, 04 Nov 2022 17:19:10 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH v5 5/6] clk: wpcm450: Add Nuvoton WPCM450 clock/reset controller driver Date: Fri, 4 Nov 2022 17:18:49 +0100 Message-Id: <20221104161850.2889894-6-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104161850.2889894-1-j.neuschaefer@gmx.net> References: <20221104161850.2889894-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:/76Kmmk0ThmjT41TrN6EY1x/On2WFUpm8Lg4RAp+axxh+1aG2aJ pnbGat0YxoNl2/79hD19CpiSKfgsq7Kp9V/ytFwlFqHaKZz8R5f+u8YPRLUKo+95flpaAKv IykChka8ooiBaZuLHorCgyVVuSIBgRAkTvZ9KNyTZq0Gt+HWYIfKWdDGrWnlAd7DZtiju9U 7KrZO8ob+kuHdXucGvZ8g== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:vFl+7BzfaFY=;84Lx/oq9/zgO02KtCFIyM0uJdyO EXRMlkdzwTJlqFYzNFC5GGalo1PpmJan+usUt5Tu8Fvv0iz98lXGNKgtmVpN2cmSF6gqHfzfj kw8jZnRxqQY/s3CeHK8jM2jHQvUlsFAdFak+hoN9LPGDtOJp39pC9GQmqLHHxkj1o6gJbcR+W 0TnsubgiQhtLrywMwrZnxCg4J7PoU5xsH4tmT1KPOCoixqwov7BSYuN8xz+0ERg8bpTy6NL9v pWIydGfkfuQU3XIWu8k9MHPlUhcx9lMQeO1aAqsDv1maWF7fRYEcrou6V3PFmyRqyWsjfV3qH ywUjEaTRP63iklKQQQTABpX55wO13AL/Ly9LYog/kPT3faEo62/nPZziL8IsPrip6jF0Usb3M 8czWqHP/VNcUkUAmbRtA5ayWsEuUmWYuqougoxbmFFB4R805dBCeTbVR0E4ohgS4PtMIa3Omn U2mrmrjEol059kMGgU2QRK6pv63WBxvWwAbdHcy49RQBjkB17HpbdvPBwkncuzBe0L95q35y1 YRjbevCzeW+WXksNC1OCAjrSSy3sdHUJSWd33jVqSToOS6X2bkKsAvA3NicBI+hYvhYJfHoH1 8cuGtzbdHaQkgAaseJtH9PwFN4QBglrjo8SqfvLFboEgc+N+olrok0IRq+5uQu650xD/qF2oT LZAEbdHyxOV0IH/NUT2K/hVfx8a9L6BCq4di2h4cXO1ZPwXwSReQftMIf5SqAQ50OY41q62Rk DwChB4GvgWauhJn8mAhE6zwy1miitE9pTI6z6RzBlsOvteEtsObl8OrIZCaqS6VM75+grIeDH dur/73+RYlp7J16J7OOUOuKZPa25ma65xaT43O8+Dhc5nf3Im+Sq/T4c/Y4Xu+43/Yct4VA04 ddH2Uw5ndN2ec948UsoO88iSXdssU9woZN/sXvAwBZt9d3u6CTY44XeJbboYmpAX8PQU27L24 q/UcQgMSpe4IrFZJayaDD83ehVI= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This driver implements the following features w.r.t. the clock and reset controller in the WPCM450 SoC: - It calculates the rates for all clocks managed by the clock controller - It leaves the clock tree mostly unchanged, except that it enables/ disables clock gates based on usage. - It exposes the reset lines managed by the controller using the Generic Reset Controller subsystem NOTE: If the driver and the corresponding devicetree node are present, the driver will disable "unused" clocks. This is problem until the clock relations are properly declared in the devicetree (in a later patch). Until then, the clk_ignore_unused kernel parameter can be used as a workaround. Signed-off-by: Jonathan Neuschäfer --- v5: - Switch to using clk_parent_data v4: - https://lore.kernel.org/lkml/20220610072141.347795-6-j.neuschaefer@gmx.net/ - Fix reset controller initialization v3: - https://lore.kernel.org/lkml/20220508194333.2170161-7-j.neuschaefer@gmx.net/ - Change reference clock name from "refclk" to "ref" - Remove unused variable in return path of wpcm450_clk_register_pll - Remove unused divisor tables v2: - https://lore.kernel.org/lkml/20220429172030.398011-7-j.neuschaefer@gmx.net/ - no changes --- drivers/clk/Makefile | 1 + drivers/clk/clk-wpcm450.c | 375 ++++++++++++++++++++++++++++++++++++++ drivers/reset/Kconfig | 2 +- 3 files changed, 377 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/clk-wpcm450.c -- 2.35.1 diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e3ca0d058a256..b58352d4d615d 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -75,6 +75,7 @@ obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_VC7) += clk-versaclock7.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o +obj-$(CONFIG_ARCH_WPCM450) += clk-wpcm450.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o # please keep this section sorted lexicographically by directory path name diff --git a/drivers/clk/clk-wpcm450.c b/drivers/clk/clk-wpcm450.c new file mode 100644 index 0000000000000..b5e81b3b6b982 --- /dev/null +++ b/drivers/clk/clk-wpcm450.c @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Nuvoton WPCM450 clock and reset controller driver. + * + * Copyright (C) 2022 Jonathan Neuschäfer + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct wpcm450_clk_pll { + struct clk_hw hw; + void __iomem *pllcon; + u8 flags; +}; + +#define to_wpcm450_clk_pll(_hw) container_of(_hw, struct wpcm450_clk_pll, hw) + +#define PLLCON_FBDV GENMASK(24, 16) +#define PLLCON_PRST BIT(13) +#define PLLCON_PWDEN BIT(12) +#define PLLCON_OTDV GENMASK(10, 8) +#define PLLCON_INDV GENMASK(5, 0) + +static unsigned long wpcm450_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + unsigned long fbdv, indv, otdv; + u64 rate; + u32 pllcon; + + if (parent_rate == 0) { + pr_err("%s: parent rate is zero", __func__); + return 0; + } + + pllcon = readl_relaxed(pll->pllcon); + + indv = FIELD_GET(PLLCON_INDV, pllcon) + 1; + fbdv = FIELD_GET(PLLCON_FBDV, pllcon) + 1; + otdv = FIELD_GET(PLLCON_OTDV, pllcon) + 1; + + rate = (u64)parent_rate * fbdv; + do_div(rate, indv * otdv); + + return rate; +} + +static int wpcm450_clk_pll_is_enabled(struct clk_hw *hw) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + u32 pllcon; + + pllcon = readl_relaxed(pll->pllcon); + + return !(pllcon & PLLCON_PRST); +} + +static void wpcm450_clk_pll_disable(struct clk_hw *hw) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + u32 pllcon; + + pllcon = readl_relaxed(pll->pllcon); + pllcon |= PLLCON_PRST | PLLCON_PWDEN; + writel(pllcon, pll->pllcon); +} + +static const struct clk_ops wpcm450_clk_pll_ops = { + .recalc_rate = wpcm450_clk_pll_recalc_rate, + .is_enabled = wpcm450_clk_pll_is_enabled, + .disable = wpcm450_clk_pll_disable +}; + +static struct clk_hw * +wpcm450_clk_register_pll(void __iomem *pllcon, const char *name, + const struct clk_parent_data *parent, unsigned long flags) +{ + struct wpcm450_clk_pll *pll; + struct clk_init_data init = {}; + int ret; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &wpcm450_clk_pll_ops; + init.parent_data = parent; + init.num_parents = 1; + init.flags = flags; + + pll->pllcon = pllcon; + pll->hw.init = &init; + + ret = clk_hw_register(NULL, &pll->hw); + if (ret) { + kfree(pll); + return ERR_PTR(ret); + } + + return &pll->hw; +} + +#define REG_CLKEN 0x00 +#define REG_CLKSEL 0x04 +#define REG_CLKDIV 0x08 +#define REG_PLLCON0 0x0c +#define REG_PLLCON1 0x10 +#define REG_PMCON 0x14 +#define REG_IRQWAKECON 0x18 +#define REG_IRQWAKEFLAG 0x1c +#define REG_IPSRST 0x20 + +struct wpcm450_pll_data { + const char *name; + struct clk_parent_data parent; + unsigned int reg; + unsigned long flags; +}; + +static const struct wpcm450_pll_data pll_data[] = { + { "pll0", { .name = "ref" }, REG_PLLCON0, 0 }, + { "pll1", { .name = "ref" }, REG_PLLCON1, 0 }, +}; + +struct wpcm450_clksel_data { + const char *name; + const struct clk_parent_data *parents; + unsigned int num_parents; + const u32 *table; + int shift; + int width; + int index; + unsigned long flags; +}; + +static const u32 parent_table[] = { 0, 1, 2 }; + +static const struct clk_parent_data default_parents[] = { + { .name = "pll0" }, + { .name = "pll1" }, + { .name = "ref" }, +}; + +static const struct clk_parent_data huart_parents[] = { + { .name = "ref" }, + { .name = "refdiv2" }, +}; + +static const struct wpcm450_clksel_data clksel_data[] = { + { "cpusel", default_parents, ARRAY_SIZE(default_parents), + parent_table, 0, 2, -1, CLK_IS_CRITICAL }, + { "clkout", default_parents, ARRAY_SIZE(default_parents), + parent_table, 2, 2, -1, 0 }, + { "usbphy", default_parents, ARRAY_SIZE(default_parents), + parent_table, 6, 2, -1, 0 }, + { "uartsel", default_parents, ARRAY_SIZE(default_parents), + parent_table, 8, 2, WPCM450_CLK_USBPHY, 0 }, + { "huartsel", huart_parents, ARRAY_SIZE(huart_parents), + parent_table, 10, 1, -1, 0 }, +}; + +static const struct clk_div_table div_fixed2[] = { + { .val = 0, .div = 2 }, + { } +}; + +struct wpcm450_clkdiv_data { + const char *name; + struct clk_parent_data parent; + int div_flags; + const struct clk_div_table *table; + int shift; + int width; + unsigned long flags; +}; + +static struct wpcm450_clkdiv_data clkdiv_data_early[] = { + { "refdiv2", { .name = "ref" }, 0, div_fixed2, 0, 0 }, +}; + +static const struct wpcm450_clkdiv_data clkdiv_data[] = { + { "cpu", { .name = "cpusel" }, 0, div_fixed2, 0, 0, CLK_IS_CRITICAL }, + { "adcdiv", { .name = "ref" }, CLK_DIVIDER_POWER_OF_TWO, NULL, 28, 2, 0 }, + { "apb", { .name = "ahb" }, CLK_DIVIDER_POWER_OF_TWO, NULL, 26, 2, 0 }, + { "ahb", { .name = "cpu" }, CLK_DIVIDER_POWER_OF_TWO, NULL, 24, 2, 0 }, + { "uart", { .name = "uartsel" }, 0, NULL, 16, 4, 0 }, + { "ahb3", { .name = "ahb" }, CLK_DIVIDER_POWER_OF_TWO, NULL, 8, 2, 0 }, +}; + +struct wpcm450_clken_data { + const char *name; + struct clk_parent_data parent; + int bitnum; + unsigned long flags; +}; + +static const struct wpcm450_clken_data clken_data[] = { + { "fiu", { .name = "ahb3" }, WPCM450_CLK_FIU, 0 }, + { "xbus", { .name = "ahb3" }, WPCM450_CLK_XBUS, 0 }, + { "kcs", { .name = "apb" }, WPCM450_CLK_KCS, 0 }, + { "shm", { .name = "ahb3" }, WPCM450_CLK_SHM, 0 }, + { "usb1", { .name = "ahb" }, WPCM450_CLK_USB1, 0 }, + { "emc0", { .name = "ahb" }, WPCM450_CLK_EMC0, 0 }, + { "emc1", { .name = "ahb" }, WPCM450_CLK_EMC1, 0 }, + { "usb0", { .name = "ahb" }, WPCM450_CLK_USB0, 0 }, + { "peci", { .name = "apb" }, WPCM450_CLK_PECI, 0 }, + { "aes", { .name = "apb" }, WPCM450_CLK_AES, 0 }, + { "uart0", { .name = "uart" }, WPCM450_CLK_UART0, 0 }, + { "uart1", { .name = "uart" }, WPCM450_CLK_UART1, 0 }, + { "smb2", { .name = "apb" }, WPCM450_CLK_SMB2, 0 }, + { "smb3", { .name = "apb" }, WPCM450_CLK_SMB3, 0 }, + { "smb4", { .name = "apb" }, WPCM450_CLK_SMB4, 0 }, + { "smb5", { .name = "apb" }, WPCM450_CLK_SMB5, 0 }, + { "huart", { .name = "huartsel" }, WPCM450_CLK_HUART, 0 }, + { "pwm", { .name = "apb" }, WPCM450_CLK_PWM, 0 }, + { "timer0", { .name = "refdiv2" }, WPCM450_CLK_TIMER0, 0 }, + { "timer1", { .name = "refdiv2" }, WPCM450_CLK_TIMER1, 0 }, + { "timer2", { .name = "refdiv2" }, WPCM450_CLK_TIMER2, 0 }, + { "timer3", { .name = "refdiv2" }, WPCM450_CLK_TIMER3, 0 }, + { "timer4", { .name = "refdiv2" }, WPCM450_CLK_TIMER4, 0 }, + { "mft0", { .name = "apb" }, WPCM450_CLK_MFT0, 0 }, + { "mft1", { .name = "apb" }, WPCM450_CLK_MFT1, 0 }, + { "wdt", { .name = "refdiv2" }, WPCM450_CLK_WDT, 0 }, + { "adc", { .name = "adcdiv" }, WPCM450_CLK_ADC, 0 }, + { "sdio", { .name = "ahb" }, WPCM450_CLK_SDIO, 0 }, + { "sspi", { .name = "apb" }, WPCM450_CLK_SSPI, 0 }, + { "smb0", { .name = "apb" }, WPCM450_CLK_SMB0, 0 }, + { "smb1", { .name = "apb" }, WPCM450_CLK_SMB1, 0 }, +}; + +static DEFINE_SPINLOCK(wpcm450_clk_lock); + +static void __init wpcm450_clk_init(struct device_node *clk_np) +{ + struct clk_hw_onecell_data *clk_data; + static struct clk_hw **hws; + static struct clk_hw *hw; + void __iomem *clk_base; + int i, ret; + struct reset_simple_data *reset; + + clk_base = of_iomap(clk_np, 0); + if (!clk_base) { + pr_err("%pOFP: failed to map registers\n", clk_np); + of_node_put(clk_np); + return; + } + of_node_put(clk_np); + + clk_data = kzalloc(struct_size(clk_data, hws, WPCM450_NUM_CLKS), GFP_KERNEL); + if (!clk_data) + goto err_unmap; + + clk_data->num = WPCM450_NUM_CLKS; + hws = clk_data->hws; + + for (i = 0; i < WPCM450_NUM_CLKS; i++) + hws[i] = ERR_PTR(-ENOENT); + + // PLLs + for (i = 0; i < ARRAY_SIZE(pll_data); i++) { + const struct wpcm450_pll_data *data = &pll_data[i]; + + hw = wpcm450_clk_register_pll(clk_base + data->reg, data->name, + &data->parent, data->flags); + if (IS_ERR(hw)) { + pr_info("Failed to register PLL: %pe", hw); + goto err_free; + } + } + + // Early divisors (REF/2) + for (i = 0; i < ARRAY_SIZE(clkdiv_data_early); i++) { + const struct wpcm450_clkdiv_data *data = &clkdiv_data_early[i]; + + hw = clk_hw_register_divider_table_parent_data(NULL, data->name, &data->parent, + data->flags, clk_base + REG_CLKDIV, + data->shift, data->width, + data->div_flags, data->table, + &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register div table: %pe\n", hw); + goto err_free; + } + } + + // Selects/muxes + for (i = 0; i < ARRAY_SIZE(clksel_data); i++) { + const struct wpcm450_clksel_data *data = &clksel_data[i]; + + hw = clk_hw_register_mux_parent_data(NULL, data->name, data->parents, + data->num_parents, data->flags, + clk_base + REG_CLKSEL, data->shift, + data->width, 0, + &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register mux: %pe\n", hw); + goto err_free; + } + if (data->index >= 0) + clk_data->hws[data->index] = hw; + } + + // Divisors + for (i = 0; i < ARRAY_SIZE(clkdiv_data); i++) { + const struct wpcm450_clkdiv_data *data = &clkdiv_data[i]; + + hw = clk_hw_register_divider_table_parent_data(NULL, data->name, &data->parent, + data->flags, clk_base + REG_CLKDIV, + data->shift, data->width, + data->div_flags, data->table, + &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register divider: %pe\n", hw); + goto err_free; + } + } + + // Enables/gates + for (i = 0; i < ARRAY_SIZE(clken_data); i++) { + const struct wpcm450_clken_data *data = &clken_data[i]; + + hw = clk_hw_register_gate_parent_data(NULL, data->name, &data->parent, data->flags, + clk_base + REG_CLKEN, data->bitnum, + data->flags, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register gate: %pe\n", hw); + goto err_free; + } + clk_data->hws[data->bitnum] = hw; + } + + ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get, clk_data); + if (ret) + pr_err("Failed to add DT provider: %d\n", ret); + + // Reset controller + reset = kzalloc(sizeof(*reset), GFP_KERNEL); + if (!reset) + goto err_free; + reset->rcdev.owner = THIS_MODULE; + reset->rcdev.nr_resets = WPCM450_NUM_RESETS; + reset->rcdev.ops = &reset_simple_ops; + reset->rcdev.of_node = clk_np; + reset->membase = clk_base + REG_IPSRST; + ret = reset_controller_register(&reset->rcdev); + if (ret) + pr_err("Failed to register reset controller: %d\n", ret); + + of_node_put(clk_np); + return; + +err_free: + kfree(clk_data->hws); +err_unmap: + iounmap(clk_base); + of_node_put(clk_np); +} + +CLK_OF_DECLARE(wpcm450_clk_init, "nuvoton,wpcm450-clk", wpcm450_clk_init); diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index de176c2fbad96..de5662830fce8 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -208,7 +208,7 @@ config RESET_SCMI config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT - default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC + default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC || ARCH_NPCM depends on HAS_IOMEM help This enables a simple reset controller driver for reset lines that From patchwork Fri Nov 4 16:18:50 2022 Content-Type: text/plain; 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Sat, 5 Nov 2022 03:19:42 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1667578751; bh=MBljRn36u0FL6eNZY6eErtpM03PtwqJkbltkRok4Li4=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=b7s0Z+KTIeqEHxHDUdWI9aKPAt+V65qGQebEI6Z3VCLgoEt+ntJjGUdU+DWWYBDiS VMvuhSZimoXNVhLzUtTGaqVT0QeOGAjvQ+ipYZ9VO/wJxH3y0IrfzeDI9engdAKrMT 0NPblUT8o/V7j6VZQnXBNmzTfG58pWA1g14rKHOCwHksTepTycL4kVijVCps9nlPDY +DCBeFKr5laZQ8Y60lIZ9OANqszQ3//Aa+vmFxqk0tIPr2g2NhU2wfcEgoHTfSVcz7 haoh9VWJ0xBLxWscW2oRn9V2Uobk5U/xq+wdf2k6Rmk+a1n5FhtqE+ooVS9LNbJcQy ixD0He1C55ugA== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([95.223.44.31]) by mail.gmx.net (mrgmx005 [212.227.17.190]) with ESMTPSA (Nemesis) id 1M8ykW-1oup9l2QBK-0065Zs; Fri, 04 Nov 2022 17:19:11 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH v5 6/6] [NOT FOR MERGE] ARM: dts: wpcm450: Switch clocks to clock controller Date: Fri, 4 Nov 2022 17:18:50 +0100 Message-Id: <20221104161850.2889894-7-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104161850.2889894-1-j.neuschaefer@gmx.net> References: <20221104161850.2889894-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:MYaeCPeDHwfn24gZVmiUqk9z7xM6e/jUPy6MKhIikdpA3HBDwFz UPp6tSuHKU/z7b7PsJjllo3vmeFJZptVEU2QXAHNiY2I8AJkob0mzz/qwVYoQJYbkBAD+Dk xKVhac7D6yIJca8gtyFgqTjzTz2zPPm3I1es/04qTDxDscDKf0doEVfyMw93mvBqAG0LFoM 3Ng60zXjhmxenOm0K21iw== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:H9UjfNO3BD0=;kgrWtE3l80XGZSPTutt39o5kwnt tMldVm6TmhS9PqJSDVDvROfSM4rYukkyJAsxSKKPi7dgzvIG3GUYsHuW/dOdqn2Cow3EpwyxM 5Iy3vl+0G2Jr2LvKUHz5sRCAZgpn6HZSyUhHYMPCdhzUbWu1mDggnQpD9r/AXNAzi/ZDc7/ge 5i1w0qZcYXrUu3eKlynm9xXpDWfRmS/MoK7Z7bUzqnwlJR8KsIEkNPR+CuLS6zahqHTpFTgs4 n9Ly50nI9gdX5MTw0gO/bqtljAnVSk+U8/MQu1wKQ1bD0rJ8087Xx8MSB448YP7lUNQoP9ElD 3mLkuj+bdlA9ukKpXeJ0EUV9owNOg1kaOdzpmir3KWddJValLUIeWAWKBFVkExzWB7Pdt0wAu N/Xzdvh3kc3ueS2J+tfaa7mfQ+Bl9B2Quuw6YPM/ViekkY06/6wQmyRX9L7uoiFDuCkzd6XI6 L+5WMZJfyrggVRcdiDwdTfDTF7DENd+c9EE9Iuwz5q0EozRzkPV0SMcrbrow5blKiLUNrFAd1 67fyj8RXn8Z1VuVk16Stlk62ScSoTfpbyIZuPQrrKiT+RizvhX9hSGr7z8+OYiKZa1zcrWUU4 zNZFT4PLC5wClZBT872ZdEUOtEj5G8uqMO9tzwrhA66deLNIUASfNDqbeapanb57mm8e20SPx 3q6c9LfFN4DraqBEL1q0QZvp5GAfQGafrEPYLkCog9K5sTbvLe6VTXNckL9bjJ2D5Y4bOAGLw BLSOkOWQy81gdBvzYv2RQ0QeIR2pjNFe7G/XbLMyL0W3GLq+2MjvcopTD0UwJhHZfWXsTz4AG wEfY7ZPT3FGErm+ZfrptAl8C/Pp4psjCHlo9Yjr4BVygnMKZXjVNwCgY0uSNP7cuKFPFaNLox fJegGfD5OF89PN89qdPpOi5miGgk2tj1oIDBR6dQKXILGaDGknOW0kFYBw5sutRLtUgFZBlCD EQ5XFqTKKdSMCyOzz4uuXDZUopg= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Krzysztof Kozlowski , Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This change is incompatible with older kernels because it requires the clock controller driver, but I think that's acceptable because WPCM450 support is generally still in an early phase. Signed-off-by: Jonathan Neuschäfer --- This patch is currently only for demonstration purposes, as it will break the build if applied in parallel (going through different maintainer trees) with the other patches in this series. I will resend it once the other patches have been merged. v2-v5: - no changes --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) -- 2.35.1 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index 332cc222c7dc5..439f9047ad651 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -2,6 +2,7 @@ // Copyright 2021 Jonathan Neuschäfer #include +#include / { compatible = "nuvoton,wpcm450"; @@ -30,13 +31,6 @@ cpu@0 { }; }; - clk24m: clock-24mhz { - /* 24 MHz dummy clock */ - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - refclk: clock-48mhz { /* 48 MHz reference oscillator */ compatible = "fixed-clock"; @@ -71,7 +65,7 @@ serial0: serial@b8000000 { reg = <0xb8000000 0x20>; reg-shift = <2>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_UART0>; pinctrl-names = "default"; pinctrl-0 = <&bsp_pins>; status = "disabled"; @@ -82,7 +76,7 @@ serial1: serial@b8000100 { reg = <0xb8000100 0x20>; reg-shift = <2>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_UART1>; status = "disabled"; }; @@ -90,14 +84,18 @@ timer0: timer@b8001000 { compatible = "nuvoton,wpcm450-timer"; interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb8001000 0x1c>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_TIMER0>, + <&clk WPCM450_CLK_TIMER1>, + <&clk WPCM450_CLK_TIMER2>, + <&clk WPCM450_CLK_TIMER3>, + <&clk WPCM450_CLK_TIMER4>; }; watchdog0: watchdog@b800101c { compatible = "nuvoton,wpcm450-wdt"; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb800101c 0x4>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_WDT>; }; aic: interrupt-controller@b8002000 {