From patchwork Fri Nov 4 16:18:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1699729 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=s31663417 header.b=QctwYSyn; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4N3m6q2d9bz23ls for ; Sat, 5 Nov 2022 03:19:47 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231887AbiKDQTo (ORCPT ); Fri, 4 Nov 2022 12:19:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231812AbiKDQTm (ORCPT ); Fri, 4 Nov 2022 12:19:42 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F129F2AC7B; Fri, 4 Nov 2022 09:19:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1667578743; bh=Pw4CakiY0E1l+i7XqKoO2ReaXNSJlyEur6HQ6/k4BHs=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=QctwYSynsohZyjY1O+iFjG/VhtoyEF2KswIA8ztlXiaJJVToNlAdm98TXLeemI1v3 n24p0xasgRuE22cEs1q5OYAtYNb2zmSQXT8q1zfRNCJaPhT9oEeecI21ELoMigKbFV FVkHlq5aMk/AtZ57fDWIjqwSkr9Uvo4aU8nT/7VM/Q8G8BJThH6tspmXV6TYeCIvWt CFWCT0iCvITgZTD6tDIKpFNpeuRmr8/oqi2peNIVrTu84awV6wmLGRGZC9lJTdDi1H qYk0OWza4Axjx28ChmMpMHK4sZpDQoNlLKrzDJtw9wweG1EKwBUXXKCZHzNzPf7e55 14sSVtAVyCWQw== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([95.223.44.31]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1Mr9Bu-1pLKGe41mo-00oCsy; Fri, 04 Nov 2022 17:19:03 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski Subject: [PATCH v5 1/6] dt-bindings: timer: nuvoton,npcm7xx-timer: Allow specifying all clocks Date: Fri, 4 Nov 2022 17:18:45 +0100 Message-Id: <20221104161850.2889894-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104161850.2889894-1-j.neuschaefer@gmx.net> References: <20221104161850.2889894-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:u1a9x+P0LGwj/elnlSQC4Rx5lPLQ1qTTs5cfZngE+CoU5yTyC87 7y2UAeUNkYVbkXUH3J5qmFUhmm/US72SI74GTLRukaxtFj619WmIARkln8jqocyFcmOefg0 veZ1EcslZPz4kOWtZCF5IiFFD2YiVSCNEZBnynlWavbkCnuxxNLA2oUeL1xiOixqcrMIvRO 9kvRgOBKnMDxzk9jCkzgg== UI-OutboundReport: notjunk:1;M01:P0:HXBfJJuJpek=;Vm/3v2yoTR9tvTyf0zQzVJ6mr7g j9qBisOmMdmJ78+KVTgWkso50NZ7euWq87LZyndvDulxwFk8ZKvXhJK94tk+8LqmqEgyUyEPF dwFZEWVwytLaO5nSmqhfU3ZC/Pzi0SymaNvxe6ONpHTja+stmYFFMALAK0wrri3OpDP2KQz4i IeWln6TbekfMqjSbYVFwqz0HHP8eB2vtzF6PT3/lF3oQt+6chmQIJ6rMFfgXigvnwbr0i3U4P 2axe9fzKRkQJbApO2qEK/6g52Qwwy2E4WLEahIH+PKJ007QqRcCKet76uKWnry7R88WodjYY5 CGG2sDyrbw2q93Yzik+kHnt29/come56auSrCeNstBieHsSA1ts2tOlfT4UCD8AJebwVfg1/d UI2NdxW6GvDP/L3zwt/8/UYqearH5tB8Q/s53T7IpRQRbPhJqtWm3c6+ZQ+MEjuCY2vv0KM+x VdtSOpoM9rssXV9WRwDCAM1B5uQ+qyXWcKWQeTefTs7IKYvyOeqTvNO9sIXxkkuJpOr4gHXB2 ExWZFCdkFo9EidrS3oxopvH5DUI/+XFxJ0z8PQmDutv6lQei0WE6DybaCtZaYBRo+T/IlAnKB e5N73REVdWFrUx1+g9x1ItP9WET53VWnDMtzD78ogdZc4iUYmiJ18p7/mg4fpcUHWTTMnmJcA 3U2K3zcv20AqjZQlP3qyMlWOaMFcMk48cXxozTP7YvAnuimjIed2s3bQVU3Zlz3Y2dXwL+Y6u cvva90QXYRiN0bex+7rC32WbNeguxbMNt7llLrll+7ZDKmywLX+XNKHtk+/8IfsHyP9PdotL3 VpgzVuE2h9V/RHtog6XxG+sRRdsZuySV9C1+tImGmhqtUaHnroFk2Wkj4Hai+cePV5YCCgy5i pO31LZWpQ7CIGF7lchSyZs3AyN/3XvyeYvAX4c5N8LE4na/4k3+80MIiA6cPR8UPQorBXyUzp jDzRqMex2oUPwWxigspAiI7cKvE= X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The timer module contains multiple timers. In the WPCM450 SoC, each timer runs off a clock can be gated individually. To model this correctly, the timer node in the devicetree needs to take multiple clock inputs. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Rob Herring --- v4-5: - no changes v3: - Add R-b tag v2: - no changes --- .../devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.35.1 diff --git a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml index 737af78ad70c3..d53e1bb98b8a6 100644 --- a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml +++ b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml @@ -25,7 +25,13 @@ properties: - description: The timer interrupt of timer 0 clocks: - maxItems: 1 + items: + - description: The reference clock for timer 0 + - description: The reference clock for timer 1 + - description: The reference clock for timer 2 + - description: The reference clock for timer 3 + - description: The reference clock for timer 4 + minItems: 1 required: - compatible From patchwork Fri Nov 4 16:18:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1699730 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=s31663417 header.b=ddRWtqOt; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4N3m6s0pFZz23ls for ; Sat, 5 Nov 2022 03:19:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231971AbiKDQTr (ORCPT ); Fri, 4 Nov 2022 12:19:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231855AbiKDQTn (ORCPT ); Fri, 4 Nov 2022 12:19:43 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A18E42D1C8; Fri, 4 Nov 2022 09:19:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1667578747; bh=kK+KEXKQcLOuTuT8IaDPuSfjwdIMIAIJT/BtBjqbAK4=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=ddRWtqOtsyOr/kez7rLUL/SHpm9ACTax43TTdZXaq8uTD9MHzIayT43Q3sASHFE/5 EybIU/4DII1l/UPv2DwhOCmH/lS4gjJftaOCdrm0fyorkCekIYQBT+6APHqIrusHCG FtL9JznpbC1XnWY/aczi3/wcYjgjWDK5sVfzWiwS+1hVf8rUNc6bARhGakJJ/Q5R3a F2tW8BQTU/chDFhh9J1dslKgTEKZWNH/05sS8dV4Y8woLqW024ikcDxFShSmKZpxCo sa3LDGB7awAOExnVhtYUyVUEJe9bRTH5wG8hchgLeOPCWrtzZvZ0a15Yv1vMC07lnL +7jKU2yeRmkMg== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([95.223.44.31]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MUXtY-1oQcot1aBk-00QQdk; Fri, 04 Nov 2022 17:19:07 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck , Krzysztof Kozlowski , Krzysztof Kozlowski Subject: [PATCH v5 3/6] dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller Date: Fri, 4 Nov 2022 17:18:47 +0100 Message-Id: <20221104161850.2889894-4-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104161850.2889894-1-j.neuschaefer@gmx.net> References: <20221104161850.2889894-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:Q/MRyQzs4UmAld8Aqho5hQzCgQujH0HLFpkNasG2BgxnN/PLjA7 4EM0Ovl4uGOM9MLk4YhIcyfw1+S7s5YyAxsKxQhHCSG0qlLr9vv89exHE6mq24z/8uqM1wS yc8Q9SogcBP882BHhubmb/8NZZig+uT9SBKlWPJ+yqPMzTMTojjhNo4xankKs+ILuBAas0G ftNty+6PgZbodl8F8epHg== UI-OutboundReport: notjunk:1;M01:P0:F05KtP1a8bw=;zprdSDIHjVY9+z5ZfevBy1dfzUI RULmQQaUeJ+JS2rHOAGJXxSRZ+43XUlNX5gN7I++B1hQbHwppQ4TJ2e1Bqe+7zKXI29ngck3M JtwqzuBfAiZh+/OMvMZARhRVOIjWrVnRPgRlwnTDPc230MfLLGgObsH/YJ53Y7DLoKBwE5MA6 oUPo80XViKP3mL6IjsHQxQodQk2U8IpqIbYSaB6ZjhDLKfky7hgm0IDmoS+MJydQJ4OzsZ0xH HffpQKrUDRTWWE7GhcCutEruJg1nA3hioYivWjzjHHtuIuzLl6QjB1Hj7/VNxKhgn1fE19p6D KvFk3bTViCRTCbmZomuw1ol4TFcshWnaMcIUHcFAO4yhB6j0g/OWs96iIYqgaYhseUKolAuca 2rVsZHlJGpe9RlGOuo9pwd2W9ydg+3heZLUkdF/Sbz71lBUZziobxnDjmvINzvPPeXlFkxWmp b67aNiZgEfJu9y7L9cdBZo8ztEtL4fJwk4HG/R/9GWxn8QfhJucGwcNJ1USkCyr+ei15/ef/q vHoxn4u/aeuc3d+Hcftb22iY2ZwsdZzZ8pXQIMAIyLkyr25YESQZ5HE7dYHPHltFq+/P5b2tG wZSds5CPSlA9XDNHYMpjwMb0kL2I1/rNswmrJb7vcLr7izZnJUpEeJi2CpLJiNaBWXaUuShez LtzFzblkd7oebF93Zg9MrbwBnZjc7iTrBaMjcXm1o2Kkofglfs1xzAkVEB/IwLkEEg0SbYH48 RW+PrsRJpPDwBB/WXFI12Mn2L9Wu2k07zUCsMmmRZrnAYlvZrZjFeF9mGsYHCVmYNMBmWRnds fy97RXVMvi+ZO00KKlvVaG2HOQxA2fdpMP9j4v2kAi2rl/b4Tod9CJ7jPjiC4UbQP+Dbdf+pi /eIcQhfqVPgc6x9PF23mHj5a4jnNkF92Jp1RMZcIf9Jj0DNez+oEP7GxUlH5fR6AGONebP8oM c06Q+g== X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Nuvoton WPCM450 SoC has a combined clock and reset controller. Add a devicetree binding for it, as well as definitions for the bit numbers used by it. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Krzysztof Kozlowski --- v5: - no changes v4: - https://lore.kernel.org/lkml/20220610072141.347795-4-j.neuschaefer@gmx.net/ - Add R-b tag v3: - Change clock-output-names and clock-names from "refclk" to "ref", suggested by Krzysztof Kozlowski v2: - https://lore.kernel.org/lkml/20220429172030.398011-5-j.neuschaefer@gmx.net/ - Various improvements, suggested by Krzysztof Kozlowski v1: - https://lore.kernel.org/lkml/20220422183012.444674-5-j.neuschaefer@gmx.net/ --- .../bindings/clock/nuvoton,wpcm450-clk.yaml | 66 ++++++++++++++++++ .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 +++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h -- 2.35.1 diff --git a/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml new file mode 100644 index 0000000000000..525024a58df4c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,wpcm450-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 clock controller + +maintainers: + - Jonathan Neuschäfer + +description: + The clock controller of the Nuvoton WPCM450 SoC supplies clocks and resets to + the rest of the chip. + +properties: + compatible: + const: nuvoton,wpcm450-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference clock oscillator (should be 48 MHz) + + clock-names: + items: + - const: ref + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + - | + #include + #include + + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-output-names = "ref"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + clk: clock-controller@b0000200 { + reg = <0xb0000200 0x100>; + compatible = "nuvoton,wpcm450-clk"; + clocks = <&refclk>; + clock-names = "ref"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/nuvoton,wpcm450-clk.h b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h new file mode 100644 index 0000000000000..86e1c895921b7 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H +#define _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H + +/* Clocks based on CLKEN bits */ +#define WPCM450_CLK_FIU 0 +#define WPCM450_CLK_XBUS 1 +#define WPCM450_CLK_KCS 2 +#define WPCM450_CLK_SHM 4 +#define WPCM450_CLK_USB1 5 +#define WPCM450_CLK_EMC0 6 +#define WPCM450_CLK_EMC1 7 +#define WPCM450_CLK_USB0 8 +#define WPCM450_CLK_PECI 9 +#define WPCM450_CLK_AES 10 +#define WPCM450_CLK_UART0 11 +#define WPCM450_CLK_UART1 12 +#define WPCM450_CLK_SMB2 13 +#define WPCM450_CLK_SMB3 14 +#define WPCM450_CLK_SMB4 15 +#define WPCM450_CLK_SMB5 16 +#define WPCM450_CLK_HUART 17 +#define WPCM450_CLK_PWM 18 +#define WPCM450_CLK_TIMER0 19 +#define WPCM450_CLK_TIMER1 20 +#define WPCM450_CLK_TIMER2 21 +#define WPCM450_CLK_TIMER3 22 +#define WPCM450_CLK_TIMER4 23 +#define WPCM450_CLK_MFT0 24 +#define WPCM450_CLK_MFT1 25 +#define WPCM450_CLK_WDT 26 +#define WPCM450_CLK_ADC 27 +#define WPCM450_CLK_SDIO 28 +#define WPCM450_CLK_SSPI 29 +#define WPCM450_CLK_SMB0 30 +#define WPCM450_CLK_SMB1 31 + +/* Other clocks */ +#define WPCM450_CLK_USBPHY 32 + +#define WPCM450_NUM_CLKS 33 + +/* Resets based on IPSRST bits */ +#define WPCM450_RESET_FIU 0 +#define WPCM450_RESET_EMC0 6 +#define WPCM450_RESET_EMC1 7 +#define WPCM450_RESET_USB0 8 +#define WPCM450_RESET_USB1 9 +#define WPCM450_RESET_AES_PECI 10 +#define WPCM450_RESET_UART 11 +#define WPCM450_RESET_MC 12 +#define WPCM450_RESET_SMB2 13 +#define WPCM450_RESET_SMB3 14 +#define WPCM450_RESET_SMB4 15 +#define WPCM450_RESET_SMB5 16 +#define WPCM450_RESET_PWM 18 +#define WPCM450_RESET_TIMER 19 +#define WPCM450_RESET_ADC 27 +#define WPCM450_RESET_SDIO 28 +#define WPCM450_RESET_SSPI 29 +#define WPCM450_RESET_SMB0 30 +#define WPCM450_RESET_SMB1 31 + +#define WPCM450_NUM_RESETS 32 + +#endif /* _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H */