From patchwork Wed Mar 7 06:32:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Gautam X-Patchwork-Id: 882428 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="kIikuM5N"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="HrtU988Y"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zx3jS54cPz9sfg for ; Wed, 7 Mar 2018 17:32:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751050AbeCGGck (ORCPT ); Wed, 7 Mar 2018 01:32:40 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:48272 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751032AbeCGGck (ORCPT ); Wed, 7 Mar 2018 01:32:40 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7B11D602A0; Wed, 7 Mar 2018 06:32:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1520404359; bh=TluDHSfEudAPzKLn5ibhlVzjPWMG6jkoc7MtgoM7J7Q=; h=From:To:Cc:Subject:Date:From; b=kIikuM5N1AoelGwBn1kumzlVmtdhKweOFcPONj55o7cQp9xmpaTKR/2MfzV/cvVf+ zaW9bikfELtOW3Hqr2z0vNEw1M2zTf+01afmlQkwdk5D179VkxbLcXNuKPjy8ZltYt pN8ormwbEvW4tTiN2VthWmtYSMu+8XiHArq437Qk= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from blr-ubuntu-41.ap.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.1 with cipher ECDHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: vivek.gautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 61D62602A0; Wed, 7 Mar 2018 06:32:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1520404358; bh=TluDHSfEudAPzKLn5ibhlVzjPWMG6jkoc7MtgoM7J7Q=; h=From:To:Cc:Subject:Date:From; b=HrtU988YfxrRWOfQ8DdY7Khr9Wwbmkh25llKLhOiocRWrwJbDq+3lbRLKZRfdTXMr 2QhC1lDC0TqnquOjjMqDJymHOqvzIxxFZ21WTvXJDnCc5bXU25zHAx0xd8xrAMOm8p tB7tVeAi0ybIRaQMUyg2IDdpQVzMuRRH+6mQfFxY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 61D62602A0 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vivek.gautam@codeaurora.org From: Vivek Gautam To: iommu@lists.linux-foundation.org, joro@8bytes.org, robin.murphy@arm.com Cc: tfiga@chromium.org, Vivek Gautam , Rob Herring , Mark Rutland , Will Deacon , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM SMMU DRIVERS) Subject: [PATCH 1/1] iommu/arm-smmu: Add support for qcom,smmu-500 variant Date: Wed, 7 Mar 2018 12:02:19 +0530 Message-Id: <20180307063219.14409-1-vivek.gautam@codeaurora.org> X-Mailer: git-send-email 2.16.1.72.g5be1f00a9a70 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Qualcomm's arm-smmu 500 implementation supports runtime pm so enable the same. Signed-off-by: Vivek Gautam --- Based on iommu/arm-smmu pm runtime support series [1]: [PATCH v8 0/5] iommu/arm-smmu: Add runtime pm/sleep support Tested on sdm845 with necessary support to enable the smmu and with necessary user. [1] https://lkml.org/lkml/2018/3/2/325 Documentation/devicetree/bindings/iommu/arm,smmu.txt | 14 ++++++++++++++ drivers/iommu/arm-smmu.c | 8 ++++++++ 2 files changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 6ea27bd4f785..0b5c6d2a9865 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -18,6 +18,7 @@ conditions. "arm,mmu-500" "cavium,smmu-v2" "qcom,-smmu-v2", "qcom,smmu-v2" + "qcom,-smmu-500", "qcom,smmu-500" depending on the particular implementation and/or the version of the architecture implemented. @@ -30,6 +31,10 @@ conditions. An example string would be - "qcom,msm8996-smmu-v2", "qcom,smmu-v2". + "qcom,smmu-500" is arm,mmu-500 implementation that supports + efficient power management by supporting smmu's state + retention. + - reg : Base address and size of the SMMU. - #global-interrupts : The number of global interrupts exposed by the @@ -179,3 +184,12 @@ conditions. <&mmcc SMMU_MDP_AHB_CLK>; clock-names = "bus", "iface"; }; + + smmu5: iommu { + compatible = "qcom,sdm845-smmu-500", "qcom,smmu-500"; + reg = <0x15000000 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + ... + }; diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 7a96c924ae22..7f52456c6b25 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -2008,6 +2008,12 @@ static const char * const qcom_smmuv2_clks[] = { "bus", "iface", }; +static const struct arm_smmu_match_data qcom_smmu500 = { + .version = ARM_SMMU_V2, + .model = ARM_MMU500, + .rpm_supported = true, +}; + static const struct arm_smmu_match_data qcom_smmuv2 = { .version = ARM_SMMU_V2, .model = QCOM_SMMUV2, @@ -2024,6 +2030,7 @@ static const struct of_device_id arm_smmu_of_match[] = { { .compatible = "arm,mmu-500", .data = &arm_mmu500 }, { .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 }, { .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 }, + { .compatible = "qcom,smmu-500", .data = &qcom_smmu500 }, { }, }; MODULE_DEVICE_TABLE(of, arm_smmu_of_match); @@ -2394,6 +2401,7 @@ IOMMU_OF_DECLARE(arm_mmu401, "arm,mmu-401"); IOMMU_OF_DECLARE(arm_mmu500, "arm,mmu-500"); IOMMU_OF_DECLARE(cavium_smmuv2, "cavium,smmu-v2"); IOMMU_OF_DECLARE(qcom_smmuv2, "qcom,smmu-v2"); +IOMMU_OF_DECLARE(qcom_smmu500, "qcom,smmu-500"); MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations"); MODULE_AUTHOR("Will Deacon ");