From patchwork Tue Sep 20 17:25:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 1680152 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=arinc9.com header.i=arinc.unal@arinc9.com header.a=rsa-sha256 header.s=zmail header.b=GCXKhOmL; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4MX7lC6QSrz1ypS for ; Wed, 21 Sep 2022 03:27:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230461AbiITR1B (ORCPT ); Tue, 20 Sep 2022 13:27:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229472AbiITR06 (ORCPT ); Tue, 20 Sep 2022 13:26:58 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E39AB5E31C; Tue, 20 Sep 2022 10:26:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1663694790; cv=none; d=zohomail.com; s=zohoarc; b=WZ9aP80pzPPeeMxqUmH4+od8fyvSU0Hvh/x5vbmxfXm056vo72upha0IOauhhGb5G+PrKb5ZyXM/zOnAQSicdB4UsmzocrvMukQMIHo0oNnlKF7z61ujJR+rAD9Wz9R1ojNtemj3nwCs+D7lir0c+VNQQBavUY53mwxNoTazNHc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1663694790; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=vXrJMHWZBZIFJYtKNziRCM6Wm5cnqBcTTG0li//8+DQ=; b=C78a5bI8FO6zDOcTSDlGPG0IlwY+wd5P195fIadEeiKOCg2Z29Ejvt/GHl7RqQjf2trwM1S0+BsXHnbFzW2oAqiesSFTtwzvl4JS8H99umQZUNXTZtVXkaSJT6LFvnPI/cyudHB0qd9IHjEtqv9YsVeqplS20ujb4AO5ttKSRBM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1663694790; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=vXrJMHWZBZIFJYtKNziRCM6Wm5cnqBcTTG0li//8+DQ=; b=GCXKhOmLRpiy+KrUTxTW95M+JHiM6jiA+q96HuFdC+D0LVOqVh1PXtWnJez2G95u kvC5zxmPwvHitETXchdlq5QpBo9QLV4sz611asoJ0McEfq0kcCGctuZrZpKiN3HeDLo ZsIMEUFS8v8sKnMHyingX7vGZVuxRRS5bNiJu7ek= Received: from arinc9-Xeront.fusolab.local (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 1663694789223795.3833959656773; Tue, 20 Sep 2022 10:26:29 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Krzysztof Kozlowski , Rob Herring , Matthias Brugger , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Thomas Bogendoerfer , Greg Kroah-Hartman , Sean Wang , Landen Chao , DENG Qingfang , Sergio Paracuellos , erkin.bozoglu@xeront.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, =?utf-8?b?QXI=?= =?utf-8?b?xLFuw6cgw5xOQUw=?= , Rob Herring Subject: [PATCH v4 net-next 01/10] dt-bindings: net: drop old mediatek bindings Date: Tue, 20 Sep 2022 20:25:47 +0300 Message-Id: <20220920172556.16557-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220920172556.16557-1-arinc.unal@arinc9.com> References: <20220920172556.16557-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Remove these old mediatek bindings which are not used. Signed-off-by: Arınç ÜNAL Acked-by: Rob Herring --- .../bindings/net/mediatek,mt7620-gsw.txt | 24 -------- .../bindings/net/ralink,rt2880-net.txt | 59 ------------------- .../bindings/net/ralink,rt3050-esw.txt | 30 ---------- 3 files changed, 113 deletions(-) delete mode 100644 Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt delete mode 100644 Documentation/devicetree/bindings/net/ralink,rt2880-net.txt delete mode 100644 Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt diff --git a/Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt b/Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt deleted file mode 100644 index 358fed2fab43..000000000000 --- a/Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt +++ /dev/null @@ -1,24 +0,0 @@ -Mediatek Gigabit Switch -======================= - -The mediatek gigabit switch can be found on Mediatek SoCs (mt7620, mt7621). - -Required properties: -- compatible: Should be "mediatek,mt7620-gsw" or "mediatek,mt7621-gsw" -- reg: Address and length of the register set for the device -- interrupts: Should contain the gigabit switches interrupt -- resets: Should contain the gigabit switches resets -- reset-names: Should contain the reset names "gsw" - -Example: - -gsw@10110000 { - compatible = "ralink,mt7620-gsw"; - reg = <0x10110000 8000>; - - resets = <&rstctrl 23>; - reset-names = "gsw"; - - interrupt-parent = <&intc>; - interrupts = <17>; -}; diff --git a/Documentation/devicetree/bindings/net/ralink,rt2880-net.txt b/Documentation/devicetree/bindings/net/ralink,rt2880-net.txt deleted file mode 100644 index 9fe1a0a22e44..000000000000 --- a/Documentation/devicetree/bindings/net/ralink,rt2880-net.txt +++ /dev/null @@ -1,59 +0,0 @@ -Ralink Frame Engine Ethernet controller -======================================= - -The Ralink frame engine ethernet controller can be found on Ralink and -Mediatek SoCs (RT288x, RT3x5x, RT366x, RT388x, rt5350, mt7620, mt7621, mt76x8). - -Depending on the SoC, there is a number of ports connected to the CPU port -directly and/or via a (gigabit-)switch. - -* Ethernet controller node - -Required properties: -- compatible: Should be one of "ralink,rt2880-eth", "ralink,rt3050-eth", - "ralink,rt3050-eth", "ralink,rt3883-eth", "ralink,rt5350-eth", - "mediatek,mt7620-eth", "mediatek,mt7621-eth" -- reg: Address and length of the register set for the device -- interrupts: Should contain the frame engines interrupt -- resets: Should contain the frame engines resets -- reset-names: Should contain the reset names "fe". If a switch is present - "esw" is also required. - - -* Ethernet port node - -Required properties: -- compatible: Should be "ralink,eth-port" -- reg: The number of the physical port -- phy-handle: reference to the node describing the phy - -Example: - -mdio-bus { - ... - phy0: ethernet-phy@0 { - phy-mode = "mii"; - reg = <0>; - }; -}; - -ethernet@400000 { - compatible = "ralink,rt2880-eth"; - reg = <0x00400000 10000>; - - #address-cells = <1>; - #size-cells = <0>; - - resets = <&rstctrl 18>; - reset-names = "fe"; - - interrupt-parent = <&cpuintc>; - interrupts = <5>; - - port@0 { - compatible = "ralink,eth-port"; - reg = <0>; - phy-handle = <&phy0>; - }; - -}; diff --git a/Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt b/Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt deleted file mode 100644 index 87e315856efa..000000000000 --- a/Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt +++ /dev/null @@ -1,30 +0,0 @@ -Ralink Fast Ethernet Embedded Switch -==================================== - -The ralink fast ethernet embedded switch can be found on Ralink and Mediatek -SoCs (RT3x5x, RT5350, MT76x8). - -Required properties: -- compatible: Should be "ralink,rt3050-esw" -- reg: Address and length of the register set for the device -- interrupts: Should contain the embedded switches interrupt -- resets: Should contain the embedded switches resets -- reset-names: Should contain the reset names "esw" - -Optional properties: -- ralink,portmap: can be used to choose if the default switch setup is - llllw or wllll -- ralink,led_polarity: override the active high/low settings of the leds - -Example: - -esw@10110000 { - compatible = "ralink,rt3050-esw"; - reg = <0x10110000 8000>; - - resets = <&rstctrl 23>; - reset-names = "esw"; - - interrupt-parent = <&intc>; - interrupts = <17>; -}; From patchwork Tue Sep 20 17:25:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 1680154 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=arinc9.com header.i=arinc.unal@arinc9.com header.a=rsa-sha256 header.s=zmail header.b=QiFheOWo; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4MX7lX0B4kz1ypS for ; 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Tue, 20 Sep 2022 10:26:37 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Krzysztof Kozlowski , Rob Herring , Matthias Brugger , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Thomas Bogendoerfer , Greg Kroah-Hartman , Sean Wang , Landen Chao , DENG Qingfang , Sergio Paracuellos , erkin.bozoglu@xeront.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, =?utf-8?b?QXI=?= =?utf-8?b?xLFuw6cgw5xOQUw=?= , Sungbo Eo , Rob Herring Subject: [PATCH v4 net-next 02/10] dt-bindings: net: dsa: mediatek,mt7530: change mt7530 switch address Date: Tue, 20 Sep 2022 20:25:48 +0300 Message-Id: <20220920172556.16557-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220920172556.16557-1-arinc.unal@arinc9.com> References: <20220920172556.16557-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the case of muxing phy0 of the MT7530 switch, the switch and the phy will have the same address on the mdio bus, 0. This causes the ethernet driver to fail since devices on the mdio bus cannot share an address. Any address can be used for the switch, therefore, change the switch address to 0x1f. Suggested-by: Sungbo Eo Signed-off-by: Arınç ÜNAL Acked-by: Rob Herring --- .../bindings/net/dsa/mediatek,mt7530.yaml | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index bc6446e1f55a..138ee6bff267 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -285,9 +285,9 @@ examples: #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@1f { compatible = "mediatek,mt7530"; - reg = <0>; + reg = <0x1f>; reset-gpios = <&pio 33 0>; @@ -346,9 +346,9 @@ examples: #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@1f { compatible = "mediatek,mt7530"; - reg = <0>; + reg = <0x1f>; mediatek,mcm; resets = <ðsys MT2701_ETHSYS_MCM_RST>; @@ -474,9 +474,9 @@ examples: #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@1f { compatible = "mediatek,mt7621"; - reg = <0>; + reg = <0x1f>; mediatek,mcm; resets = <&sysc MT7621_RST_MCM>; @@ -560,9 +560,9 @@ examples: reg = <4>; }; - switch@0 { + switch@1f { compatible = "mediatek,mt7621"; - reg = <0>; + reg = <0x1f>; mediatek,mcm; resets = <&sysc MT7621_RST_MCM>; @@ -650,9 +650,9 @@ examples: phy-mode = "rgmii"; }; - switch@0 { + switch@1f { compatible = "mediatek,mt7621"; - reg = <0>; + reg = <0x1f>; mediatek,mcm; resets = <&sysc MT7621_RST_MCM>; @@ -730,9 +730,9 @@ examples: phy-mode = "rgmii"; }; - switch@0 { + switch@1f { compatible = "mediatek,mt7621"; - reg = <0>; + reg = <0x1f>; mediatek,mcm; resets = <&sysc MT7621_RST_MCM>; From patchwork Tue Sep 20 17:25:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 1680155 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=arinc9.com header.i=arinc.unal@arinc9.com header.a=rsa-sha256 header.s=zmail header.b=EiaQkh4d; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4MX7lX3MKcz1yqF for ; Wed, 21 Sep 2022 03:27:20 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231152AbiITR1T (ORCPT ); Tue, 20 Sep 2022 13:27:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229472AbiITR1S (ORCPT ); Tue, 20 Sep 2022 13:27:18 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B1C55AC41; Tue, 20 Sep 2022 10:27:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1663694810; cv=none; d=zohomail.com; s=zohoarc; b=Vf4SWT654FdYobDvJdXk5Qbm/45ar0C8Ef6qbNZzX8An7in+9Gs1SbmlDfxCq63lgY5Gx/Z+UkOJe2FZ+dHa6Fgb0YYaYv3kyORMgyROjMhrILA4eiuyL7BKht5V64BAUddWo5mNAuNgjpgNw3ZPWM3EEFZMMTM21sFYEqE37eo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1663694810; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=q2aHD/2EQ0E3NOJZmAmLUmUUrpAWHblOhyutE0P5unM=; b=YhUNPcWi8hNKxBIlyxgHkOfXjh8EeC+FTV+tG13wj2UNK6ohCpNzM+3Rmk9Mb7TqSWfNKIR7mDvxApUiw38Bdn5g97M3NZiii46uxILHBwMphK2EqjJ2M7YFgnn6g2EECS5+/j3r1FlnrRFW/Urljbj7yvCuL58e1dM4aE1yf1E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1663694810; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=q2aHD/2EQ0E3NOJZmAmLUmUUrpAWHblOhyutE0P5unM=; b=EiaQkh4dX2Q7XjYLdtQcB/Irw5Ut8+4ukyCjOfZjfwQJqi/lr22tQfeQ7Fu9EQ3M Qu1whWvYaV9+LyB5FSoru0CKypyK0OBfcKZGYK2KpdKVB+MK8f3/89uUGtTBuHfeNzF 3YyLZNSebvjUxuarSZ9NHnq8WzY/3GUjUUfRZK4s= Received: from arinc9-Xeront.fusolab.local (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 1663694806491670.9202934830495; Tue, 20 Sep 2022 10:26:46 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Krzysztof Kozlowski , Rob Herring , Matthias Brugger , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Thomas Bogendoerfer , Greg Kroah-Hartman , Sean Wang , Landen Chao , DENG Qingfang , Sergio Paracuellos , erkin.bozoglu@xeront.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, =?utf-8?b?QXI=?= =?utf-8?b?xLFuw6cgw5xOQUw=?= , Rob Herring Subject: [PATCH v4 net-next 03/10] dt-bindings: net: dsa: mediatek,mt7530: expand gpio-controller description Date: Tue, 20 Sep 2022 20:25:49 +0300 Message-Id: <20220920172556.16557-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220920172556.16557-1-arinc.unal@arinc9.com> References: <20220920172556.16557-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Expand the description of the gpio-controller property to include the controllable pins of the MT7530 switch. The gpio-controller property is only used for the MT7530 switch. Therefore, invalidate it for the MT7531 switch. Signed-off-by: Arınç ÜNAL Acked-by: Rob Herring --- .../devicetree/bindings/net/dsa/mediatek,mt7530.yaml | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 138ee6bff267..f2e9ff3f580b 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -104,7 +104,14 @@ properties: gpio-controller: type: boolean description: - If defined, MT7530's LED controller will run on GPIO mode. + If defined, LED controller of the MT7530 switch will run on GPIO mode. + + There are 15 controllable pins. + port 0 LED 0..2 as GPIO 0..2 + port 1 LED 0..2 as GPIO 3..5 + port 2 LED 0..2 as GPIO 6..8 + port 3 LED 0..2 as GPIO 9..11 + port 4 LED 0..2 as GPIO 12..14 "#interrupt-cells": const: 1 @@ -263,6 +270,7 @@ allOf: then: $ref: "#/$defs/mt7531-dsa-port" properties: + gpio-controller: false mediatek,mcm: false - if: From patchwork Tue Sep 20 17:25:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 1680156 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=arinc9.com header.i=arinc.unal@arinc9.com header.a=rsa-sha256 header.s=zmail header.b=AevlrT3b; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4MX7lk6XVhz1ypS for ; Wed, 21 Sep 2022 03:27:30 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231237AbiITR11 (ORCPT ); Tue, 20 Sep 2022 13:27:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231240AbiITR1X (ORCPT ); Tue, 20 Sep 2022 13:27:23 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B4D96DAE4; Tue, 20 Sep 2022 10:27:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1663694815; cv=none; d=zohomail.com; s=zohoarc; b=Pf2wu6jokESlhJcfxulHpRbNn+PmkqTU30njmw7d4NG4S/hORPw1Izyw28no2ijXcKEk3WM7ww9BFjvMcQsaSyhiwdopCEQAPokKkL3JMUy0RKgsL637yob3CNq8rLFsKX2P+cm5TAkiVDODidlPmBPOFEfzN2FJMsMVSS3n9ME= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1663694815; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=rHbrnngZgX9HMOc32S4hW2g51zfVsFIeWN4epeg9j3M=; b=Jm9keUzqWrQavhSyj5NKh9h+StRgtKMZe6cR6Gd5ZaRjZv8ZirIe7oVHo4V+XsQ5GCXe5Pgc3sUPUIkS7QAd9+j2x0qs7LFpm1JlJ1J3L17ReG9HPTacunPd8/K45YS26K/1uFrwsmeakydHSFSIg5K6xyjx5UTFAnVvlt5Ley8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1663694815; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=rHbrnngZgX9HMOc32S4hW2g51zfVsFIeWN4epeg9j3M=; b=AevlrT3bT5nr7Tj36+glqQkwMeA+B4C8zFJKqTqL9fhj4RuKa4U6zp3nkk3INzun Q4dYSeev4fE9Bk+kNpHH5ExddtzsDF0R9qj5lPullN13GW4MCUadfhVgBAjl2JF7UOn G9AtVyt5D/HnZcr22ICFlNmZaAPqbpxvKqytdfQw= Received: from arinc9-Xeront.fusolab.local (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 1663694815131693.4385194837167; Tue, 20 Sep 2022 10:26:55 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Krzysztof Kozlowski , Rob Herring , Matthias Brugger , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Thomas Bogendoerfer , Greg Kroah-Hartman , Sean Wang , Landen Chao , DENG Qingfang , Sergio Paracuellos , erkin.bozoglu@xeront.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, =?utf-8?b?QXI=?= =?utf-8?b?xLFuw6cgw5xOQUw=?= Subject: [PATCH v4 net-next 04/10] dt-bindings: memory: mt7621: add syscon as compatible string Date: Tue, 20 Sep 2022 20:25:50 +0300 Message-Id: <20220920172556.16557-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220920172556.16557-1-arinc.unal@arinc9.com> References: <20220920172556.16557-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The syscon string was introduced because the mt7621 clock driver needs to read some registers creating a regmap from the syscon. The bindings were added before the clock driver was properly mainlined and at first the clock driver was using ralink architecture dependent operations rt_memc_* defined in 'arch/mips/include/asm/mach-ralink/ralink_regs.h'. This string is already there on the memory controller node on mt7621.dtsi. Add syscon as a constant string on the compatible property, now that memc became a syscon. Update the example accordingly. Fixes: 5278e4a181ff ("dt-bindings: memory: add binding for Mediatek's MT7621 SDRAM memory controller") Signed-off-by: Arınç ÜNAL Acked-by: Sergio Paracuellos --- .../bindings/memory-controllers/mediatek,mt7621-memc.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml index 85e02854f083..6ccdaf99c778 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml @@ -11,7 +11,9 @@ maintainers: properties: compatible: - const: mediatek,mt7621-memc + items: + - const: mediatek,mt7621-memc + - const: syscon reg: maxItems: 1 @@ -25,6 +27,6 @@ additionalProperties: false examples: - | memory-controller@5000 { - compatible = "mediatek,mt7621-memc"; + compatible = "mediatek,mt7621-memc", "syscon"; reg = <0x5000 0x1000>; };