From patchwork Mon Sep 19 01:11:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chong, Teik Heng" X-Patchwork-Id: 1679132 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=DM6QM4WT; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MW68s59zXz1ypM for ; Mon, 19 Sep 2022 11:12:13 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 07B3084A92; Mon, 19 Sep 2022 03:12:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="DM6QM4WT"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4FE0384BE6; Mon, 19 Sep 2022 03:12:07 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9ACBD849AA for ; Mon, 19 Sep 2022 03:12:03 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=teik.heng.chong@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663549923; x=1695085923; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=2Aw0cPuPY9lBBbPCmVoSAH1l5BY2yrU7LWwO12FGF+o=; b=DM6QM4WTL1w/ASzGJGpVEo7bptQ38HC0VHUQNQCTwLMWhRmV7bY/P9Pj FI6ijXsJ29sc1sEP4ASE1cawFsw8swjA0ooefUvwA79cDRzJNUwtyiipQ sdvNsREW/pBjasp3ikjVOaofhoYsWazgKpkAHHxpTcZKJ/foEOuo9PXTt WtZ8HvXu/4gRTgHHTbWBzVjpU+U/2mTTvpCkbs8qmzJJsLF0K6Eu16Jgf o5UwGHNSgFdjvzUJRIKb5qhMaqjU0fg4WpgArdOmLzlxe/56x3MrCa4ok zvVZJzq/2Y4OIa1y8o8vJ/XqvWr6UazDrZTzAWGOKC/Fu28A3pSYsD6Sw g==; X-IronPort-AV: E=McAfee;i="6500,9779,10474"; a="299273418" X-IronPort-AV: E=Sophos;i="5.93,325,1654585200"; d="scan'208";a="299273418" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2022 18:12:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,325,1654585200"; d="scan'208";a="863370071" Received: from pgli4336.png.intel.com ([10.221.172.41]) by fmsmga006.fm.intel.com with ESMTP; 18 Sep 2022 18:11:58 -0700 From: teik.heng.chong@intel.com To: u-boot@lists.denx.de Cc: Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang Subject: [PATCH] arm: socfpga: Add watchdog 1 support to A10 Date: Mon, 19 Sep 2022 09:11:55 +0800 Message-Id: <20220919011155.30044-1-teik.heng.chong@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Add watchdog 1 support to A10, ensure the same enable/disable process as watchdog 0. Signed-off-by: Tien Fong Chee Signed-off-by: Teik Heng Chong --- .../mach-socfpga/include/mach/base_addr_a10.h | 1 + .../include/mach/reset_manager_arria10.h | 1 + arch/arm/mach-socfpga/reset_manager_arria10.c | 21 ++++++++++++++----- arch/arm/mach-socfpga/spl_a10.c | 2 +- 4 files changed, 19 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index b947cc0729..246618f4da 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -17,6 +17,7 @@ #define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffcfe400 #define SOCFPGA_FPGAMGRREGS_ADDRESS 0xffd03000 #define SOCFPGA_L4WD0_ADDRESS 0xffd00200 +#define SOCFPGA_L4WD1_ADDRESS 0xffd00300 #define SOCFPGA_SYSMGR_ADDRESS 0xffd06000 #define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS 0xffd07000 #define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd07200 diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h index 9aacf3e2c6..53efb64234 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h @@ -13,6 +13,7 @@ void socfpga_watchdog_disable(void); void socfpga_reset_deassert_noc_ddr_scheduler(void); int socfpga_reset_deassert_bridges_handoff(void); void socfpga_reset_deassert_wd0(void); +void socfpga_reset_deassert_wd1(void); int socfpga_bridges_reset(void); #define RSTMGR_A10_STATUS 0x00 diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index 13a5cf314b..25c7291246 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -61,6 +61,9 @@ void socfpga_watchdog_disable(void) /* assert reset for watchdog */ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST, ALT_RSTMGR_PER1MODRST_WD0_SET_MSK); + + setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST, + ALT_RSTMGR_PER1MODRST_WD1_SET_MSK); } /* Release NOC ddr scheduler from reset */ @@ -116,6 +119,13 @@ void socfpga_reset_deassert_wd0(void) ALT_RSTMGR_PER1MODRST_WD0_SET_MSK); } +/* Release Watchdog 1 from reset through reset manager */ +void socfpga_reset_deassert_wd1(void) +{ + clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST, + ALT_RSTMGR_PER1MODRST_WD1_SET_MSK); +} + /* * Assert or de-assert SoCFPGA reset manager reset. */ @@ -154,15 +164,16 @@ void socfpga_per_reset(u32 reset, int set) } /* - * Assert reset on every peripheral but L4WD0. + * Assert reset on every peripheral but L4WD0 & l4WD1. * Watchdog must be kept intact to prevent glitches * and/or hangs. * For the Arria10, we disable all the peripherals except L4 watchdog0, - * L4 Timer 0, and ECC. + * L4 watchdog1, L4 Timer 0, and ECC. */ void socfpga_per_reset_all(void) { - const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) | + const u32 l4wd = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) | + 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD1)) | (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0)))); unsigned mask_ecc_ocp = ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK | @@ -174,8 +185,8 @@ void socfpga_per_reset_all(void) ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK; - /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */ - writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST); + /* disable all components except ECC_OCP, L4 Timer0, L4 WD0 & l4 WD1 */ + writel(~l4wd, socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST); setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST, ~mask_ecc_ocp); diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 96bad162df..5d661fb995 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -255,7 +255,7 @@ void board_init_f(ulong dummy) socfpga_sdram_remap_zero(); socfpga_pl310_clear(); - /* Assert reset to all except L4WD0 and L4TIMER0 */ + /* Assert reset to all except L4WD0, L4WD1 and L4TIMER0 */ socfpga_per_reset_all(); socfpga_watchdog_disable();