From patchwork Mon Sep 19 00:57:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chong, Teik Heng" X-Patchwork-Id: 1679130 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Js7Jcphp; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MW5rG4tpTz1ypM for ; Mon, 19 Sep 2022 10:57:50 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2A14484A92; Mon, 19 Sep 2022 02:57:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Js7Jcphp"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6D56884BE4; Mon, 19 Sep 2022 02:57:43 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C4BB2849AA for ; Mon, 19 Sep 2022 02:57:40 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=teik.heng.chong@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663549061; x=1695085061; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=kv1BpVgBYoLsfL1f/K57s5CHxvabd5wa8THDNab+9ho=; b=Js7JcphpNK3leKGWdivoTylLWZXuebixGBWP+LOvkvIR8zJ01oMC94mt 0fs6ECEpPbHke18N23HzlahfmiTB5ewhl1DTnbWBWPxdHbUyoYlip9qTI FNbZvas1f5/XKKLnlCQSKa2Mh6VfpLi80w/Q7XdvU08Lf8YTrS8PyyNiV POuQfuJ/oD7tkMtBVVPRLC00PFOI3R1QWoAQkwMh4CwwsRGzpZdA1qkNg mQFam9Cbdd1jbSepv6wBFAMVphloiMzOnEK+SZ2Q8X/hqClDRPcuE6TbF dA9CAXzZTdTF2/IYl+/Hx9GAB6qlFH0Z1qvJRK73m4opmfzkFc4jr60wV A==; X-IronPort-AV: E=McAfee;i="6500,9779,10474"; a="300100644" X-IronPort-AV: E=Sophos;i="5.93,325,1654585200"; d="scan'208";a="300100644" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2022 17:57:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,325,1654585200"; d="scan'208";a="569453238" Received: from pgli4336.png.intel.com ([10.221.172.41]) by orsmga003.jf.intel.com with ESMTP; 18 Sep 2022 17:57:35 -0700 From: teik.heng.chong@intel.com To: u-boot@lists.denx.de Cc: Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang Subject: [PATCH] ddr: socfpga: Improve A10 SDRAM ECC init function to support watchdog reset Date: Mon, 19 Sep 2022 08:57:29 +0800 Message-Id: <20220919005729.21002-1-teik.heng.chong@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee There is a potential risk that memset on DDR taking too long than the timeout set for watchdog, hence the function is restructured so that splitting up the DDR into chunks for memset and resetting the watchdog for each chunk memory. Signed-off-by: Tien Fong Chee Signed-off-by: Teik Heng Chong --- drivers/ddr/altera/sdram_arria10.c | 38 ++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index 4a8f8dea1c..6eb7a34bc0 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -22,6 +22,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -48,6 +49,8 @@ static u64 sdram_size_calc(void); #define CORE2SEQ_INT_REQ 0xF #define SEQ2CORE_INT_RESP_BIT 3 +#define PGTABLE_OFF 0x4000 + static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base = (void *)SOCFPGA_SDR_ADDRESS; static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base = @@ -196,19 +199,44 @@ static int sdram_is_ecc_enabled(void) /* Initialize SDRAM ECC bits to avoid false DBE */ static void sdram_init_ecc_bits(u32 size) { - icache_enable(); + u32 start, size_init, start_addr; + + start = get_timer(0); + + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = size; - memset(0, 0, 0x8000); - gd->arch.tlb_addr = 0x4000; + gd->arch.tlb_addr = gd->bd->bi_dram[0].start + PGTABLE_OFF; gd->arch.tlb_size = PGTABLE_SIZE; + memset((void *)gd->bd->bi_dram[0].start, 0, gd->arch.tlb_addr + + gd->arch.tlb_size + SZ_1K); + + icache_enable(); dcache_enable(); - printf("DDRCAL: Scrubbing ECC RAM (%i MiB).\n", size >> 20); - memset((void *)0x8000, 0, size - 0x8000); + start_addr = gd->arch.tlb_addr + gd->arch.tlb_size; + size -= (gd->arch.tlb_addr + gd->arch.tlb_size); + + printf("DDRCAL: Scrubbing ECC RAM (%d MiB).\n", size >> 20); + + + while (size > 0) { + size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size); + memset((void *)start_addr, 0, size_init); + size -= size_init; + start_addr += size_init; + WATCHDOG_RESET(); + } + flush_dcache_all(); + printf("DDRCAL: Scrubbing ECC RAM done.\n"); + dcache_disable(); + + printf("DDRCAL: SDRAM-ECC initialized success with %d ms\n", + (u32)get_timer(start)); } /* Function to startup the SDRAM*/