From patchwork Sun Sep 18 13:41:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 1679021 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=arinc9.com header.i=arinc.unal@arinc9.com header.a=rsa-sha256 header.s=zmail header.b=CJEn+fMO; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4MVprn5yYKz1yq2 for ; Sun, 18 Sep 2022 23:42:17 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229674AbiIRNmL (ORCPT ); Sun, 18 Sep 2022 09:42:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229497AbiIRNmJ (ORCPT ); Sun, 18 Sep 2022 09:42:09 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7A381A398; Sun, 18 Sep 2022 06:42:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1663508496; cv=none; d=zohomail.com; s=zohoarc; b=dVmUQhTBSDe5ZPMUoqBiOQ06ScbjNJw+8/ozGfjkPpWWtY5mzbknmo31w3UO4vfUNW/SlMC22dm6FUugllafbSTVBVFbnQzB0YiV/2drswUfzO91C0M4qukksf96lzhIpDw896rwCzMWJNWindzbjG9p0Ra2vwf75UUNCssHROs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1663508496; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=vXrJMHWZBZIFJYtKNziRCM6Wm5cnqBcTTG0li//8+DQ=; b=VL8m9OxaTrOi3YNr8LpgsZYXdePLNcHO0eEz/fNuk4eVsnsMaVfEvFQ3+St689kmPTNnBsqHmULbpnwmnqCRD62uDz2s1owkDGYms3zsqGmA3kPkbqgZHs4T3czljBdnBq7W6K5p4TZVUjI5vullORxiw2GJ56EdBfIiwNMxdhc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1663508496; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=vXrJMHWZBZIFJYtKNziRCM6Wm5cnqBcTTG0li//8+DQ=; b=CJEn+fMO5SNX2E72bLPB8zK+qs0iwPfqYxQd0AUplqVB9Lpep/SanPwk2hWEU5Vy 3x1ZoPXBU7iYT86hb1BUlhCNlPjq9QpL92GEXq6hA8cydKdyqQjd1U/Cfbpg8+Y+UWN Pm0F50qHtdv9bphWByZQGQNr7etVvy6P28mLRXkQ= Received: from arinc9-PC.lan (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 1663508495074514.8271123875563; Sun, 18 Sep 2022 06:41:35 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Krzysztof Kozlowski , Rob Herring , Matthias Brugger , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Thomas Bogendoerfer , Greg Kroah-Hartman , Sean Wang , Landen Chao , DENG Qingfang , Sergio Paracuellos , erkin.bozoglu@xeront.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, =?utf-8?b?QXI=?= =?utf-8?b?xLFuw6cgw5xOQUw=?= , Rob Herring Subject: [PATCH v3 net-next 01/10] dt-bindings: net: drop old mediatek bindings Date: Sun, 18 Sep 2022 16:41:09 +0300 Message-Id: <20220918134118.554813-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220918134118.554813-1-arinc.unal@arinc9.com> References: <20220918134118.554813-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Remove these old mediatek bindings which are not used. Signed-off-by: Arınç ÜNAL Acked-by: Rob Herring --- .../bindings/net/mediatek,mt7620-gsw.txt | 24 -------- .../bindings/net/ralink,rt2880-net.txt | 59 ------------------- .../bindings/net/ralink,rt3050-esw.txt | 30 ---------- 3 files changed, 113 deletions(-) delete mode 100644 Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt delete mode 100644 Documentation/devicetree/bindings/net/ralink,rt2880-net.txt delete mode 100644 Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt diff --git a/Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt b/Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt deleted file mode 100644 index 358fed2fab43..000000000000 --- a/Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt +++ /dev/null @@ -1,24 +0,0 @@ -Mediatek Gigabit Switch -======================= - -The mediatek gigabit switch can be found on Mediatek SoCs (mt7620, mt7621). - -Required properties: -- compatible: Should be "mediatek,mt7620-gsw" or "mediatek,mt7621-gsw" -- reg: Address and length of the register set for the device -- interrupts: Should contain the gigabit switches interrupt -- resets: Should contain the gigabit switches resets -- reset-names: Should contain the reset names "gsw" - -Example: - -gsw@10110000 { - compatible = "ralink,mt7620-gsw"; - reg = <0x10110000 8000>; - - resets = <&rstctrl 23>; - reset-names = "gsw"; - - interrupt-parent = <&intc>; - interrupts = <17>; -}; diff --git a/Documentation/devicetree/bindings/net/ralink,rt2880-net.txt b/Documentation/devicetree/bindings/net/ralink,rt2880-net.txt deleted file mode 100644 index 9fe1a0a22e44..000000000000 --- a/Documentation/devicetree/bindings/net/ralink,rt2880-net.txt +++ /dev/null @@ -1,59 +0,0 @@ -Ralink Frame Engine Ethernet controller -======================================= - -The Ralink frame engine ethernet controller can be found on Ralink and -Mediatek SoCs (RT288x, RT3x5x, RT366x, RT388x, rt5350, mt7620, mt7621, mt76x8). - -Depending on the SoC, there is a number of ports connected to the CPU port -directly and/or via a (gigabit-)switch. - -* Ethernet controller node - -Required properties: -- compatible: Should be one of "ralink,rt2880-eth", "ralink,rt3050-eth", - "ralink,rt3050-eth", "ralink,rt3883-eth", "ralink,rt5350-eth", - "mediatek,mt7620-eth", "mediatek,mt7621-eth" -- reg: Address and length of the register set for the device -- interrupts: Should contain the frame engines interrupt -- resets: Should contain the frame engines resets -- reset-names: Should contain the reset names "fe". If a switch is present - "esw" is also required. - - -* Ethernet port node - -Required properties: -- compatible: Should be "ralink,eth-port" -- reg: The number of the physical port -- phy-handle: reference to the node describing the phy - -Example: - -mdio-bus { - ... - phy0: ethernet-phy@0 { - phy-mode = "mii"; - reg = <0>; - }; -}; - -ethernet@400000 { - compatible = "ralink,rt2880-eth"; - reg = <0x00400000 10000>; - - #address-cells = <1>; - #size-cells = <0>; - - resets = <&rstctrl 18>; - reset-names = "fe"; - - interrupt-parent = <&cpuintc>; - interrupts = <5>; - - port@0 { - compatible = "ralink,eth-port"; - reg = <0>; - phy-handle = <&phy0>; - }; - -}; diff --git a/Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt b/Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt deleted file mode 100644 index 87e315856efa..000000000000 --- a/Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt +++ /dev/null @@ -1,30 +0,0 @@ -Ralink Fast Ethernet Embedded Switch -==================================== - -The ralink fast ethernet embedded switch can be found on Ralink and Mediatek -SoCs (RT3x5x, RT5350, MT76x8). - -Required properties: -- compatible: Should be "ralink,rt3050-esw" -- reg: Address and length of the register set for the device -- interrupts: Should contain the embedded switches interrupt -- resets: Should contain the embedded switches resets -- reset-names: Should contain the reset names "esw" - -Optional properties: -- ralink,portmap: can be used to choose if the default switch setup is - llllw or wllll -- ralink,led_polarity: override the active high/low settings of the leds - -Example: - -esw@10110000 { - compatible = "ralink,rt3050-esw"; - reg = <0x10110000 8000>; - - resets = <&rstctrl 23>; - reset-names = "esw"; - - interrupt-parent = <&intc>; - interrupts = <17>; -}; From patchwork Sun Sep 18 13:41:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 1679024 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=arinc9.com header.i=arinc.unal@arinc9.com header.a=rsa-sha256 header.s=zmail header.b=Z/lZ7EVW; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4MVps20C3Hz1ync for ; Sun, 18 Sep 2022 23:42:30 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229793AbiIRNm0 (ORCPT ); Sun, 18 Sep 2022 09:42:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229723AbiIRNmX (ORCPT ); Sun, 18 Sep 2022 09:42:23 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB8F81A82D; Sun, 18 Sep 2022 06:42:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1663508502; cv=none; d=zohomail.com; s=zohoarc; b=OItcQHojLQt8Xpk2H4OgBvas5Hmz21To2oy5fjVvrnkzlN3eiGBl5paxagC+Y0DWL/9/e1WK/R/XiMuFB4THFu6CvEqnny+xyLXsrVo/D0Ckq/qRGDKhXjXLeGyKsgThZ0qiUZYBQGTgBlyBH4TAH+1kssD52SVmui526gsA8Bg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1663508502; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=mv8wnCQI8K+FkvB2ZahCjYMMUvp+WpG/VEtG06Ocnio=; b=FpQdu0FgeDMcw3wK0DZrLL8gSF4hPghgUdr2rGQS3ekXvVbRHMllHMuZwwoMRj8h437T9ZUnQ450stVZ6MHC4t+82+5TxVTgImpnDBGqqjzlkNgMQ91tGdZIk5PrPOV0dVky76nBLpQo0QfbdV4GJp/Z2DUeuVaK3fvKql0vtC4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1663508502; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=mv8wnCQI8K+FkvB2ZahCjYMMUvp+WpG/VEtG06Ocnio=; b=Z/lZ7EVWbrFILGt5R6plaSvE+fsP6gxGgxfCo0dxnwh00EdMfCHKKRZ+gISGjot+ 3uINCWoixO6lM/l7BhoyAUYWLoGQTM3alwZa3Jz7uGOZwVVDiYJixKWFq5NHyyaUOuz HCsCv3tLDNy3l0U9vNywkKCgM8tT9jp+kZJQWyhY= Received: from arinc9-PC.lan (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 166350850131962.28244589605106; Sun, 18 Sep 2022 06:41:41 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Krzysztof Kozlowski , Rob Herring , Matthias Brugger , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Thomas Bogendoerfer , Greg Kroah-Hartman , Sean Wang , Landen Chao , DENG Qingfang , Sergio Paracuellos , erkin.bozoglu@xeront.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, =?utf-8?b?QXI=?= =?utf-8?b?xLFuw6cgw5xOQUw=?= , Sungbo Eo , Rob Herring Subject: [PATCH v3 net-next 02/10] dt-bindings: net: dsa: mediatek,mt7530: change mt7530 switch address Date: Sun, 18 Sep 2022 16:41:10 +0300 Message-Id: <20220918134118.554813-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220918134118.554813-1-arinc.unal@arinc9.com> References: <20220918134118.554813-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the case of muxing phy0 of the MT7530 switch, the switch and the phy will have the same address on the mdio bus, 0. This causes the ethernet driver to fail since devices on the mdio bus cannot share an address. Any address can be used for the switch, therefore, change the switch address to 0x1f. Suggested-by: Sungbo Eo Signed-off-by: Arınç ÜNAL Acked-by: Rob Herring --- .../bindings/net/dsa/mediatek,mt7530.yaml | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index f9e7b6e20b35..2c73d13adf14 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -294,9 +294,9 @@ examples: #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@1f { compatible = "mediatek,mt7530"; - reg = <0>; + reg = <0x1f>; reset-gpios = <&pio 33 0>; @@ -356,9 +356,9 @@ examples: #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@1f { compatible = "mediatek,mt7530"; - reg = <0>; + reg = <0x1f>; mediatek,mcm; resets = <ðsys MT2701_ETHSYS_MCM_RST>; @@ -486,9 +486,9 @@ examples: #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@1f { compatible = "mediatek,mt7621"; - reg = <0>; + reg = <0x1f>; mediatek,mcm; resets = <&sysc MT7621_RST_MCM>; @@ -573,9 +573,9 @@ examples: reg = <4>; }; - switch@0 { + switch@1f { compatible = "mediatek,mt7621"; - reg = <0>; + reg = <0x1f>; mediatek,mcm; resets = <&sysc MT7621_RST_MCM>; @@ -664,9 +664,9 @@ examples: phy-mode = "rgmii"; }; - switch@0 { + switch@1f { compatible = "mediatek,mt7621"; - reg = <0>; + reg = <0x1f>; mediatek,mcm; resets = <&sysc MT7621_RST_MCM>; @@ -745,9 +745,9 @@ examples: phy-mode = "rgmii"; }; - switch@0 { + switch@1f { compatible = "mediatek,mt7621"; - reg = <0>; + reg = <0x1f>; mediatek,mcm; resets = <&sysc MT7621_RST_MCM>; From patchwork Sun Sep 18 13:41:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 1679022 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=arinc9.com header.i=arinc.unal@arinc9.com header.a=rsa-sha256 header.s=zmail header.b=bJwJ9pZg; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4MVprp2FMCz1ync for ; Sun, 18 Sep 2022 23:42:18 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229533AbiIRNmM (ORCPT ); Sun, 18 Sep 2022 09:42:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229518AbiIRNmK (ORCPT ); Sun, 18 Sep 2022 09:42:10 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 817311A05D; Sun, 18 Sep 2022 06:42:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1663508508; cv=none; d=zohomail.com; s=zohoarc; b=VNFOYKWX+MAMRMNdzgDrKx77bE/I/O9IerSAcDbwIEtHWGaxGCBYIRII8e42dKUAE/3iQfUVPIaKBEe8+OkWuaV0zYf9KKulcfe+o4py1Yddz+UwFFodGEAcm+EdngcJOcP20PuGgE9cFgFLgbuVgDVidmIQq6oLMD9ys1Wekjc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1663508508; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=08pH7piTGTvh/ZeXP1Swxz+oCzEd8UkwdY3/1IA2wBY=; b=kw4QhSMI5LvrA4cW1o+4rdGR6PQ6kyL2QUCU2ZdYgSR84ZVanBnjWwxdNnt9AxNCJ5vYYzIPXiggd2vqs2kFZ8K7ZQCxfQjC+nAOToU4RhGBPP1Apz3+I/1sfSOA1PfuXrTR41LDej5HOHfJGecuecwVx6FTymPVXU/B0uGkTEk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1663508508; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=08pH7piTGTvh/ZeXP1Swxz+oCzEd8UkwdY3/1IA2wBY=; b=bJwJ9pZgGKJ2soleOcTp3Pb4A2Yc9ruWTQHVVczJjVx4FRTqUSgglQ4TXr8YqDcm PI9sMDR0Kq4k05d1/rOh0osy0YpVDB0dfhoKTqeRDEbROq3GDGY0nNl0DXaxpsm8DpI MAruco12d/4SkZYNIsL1tetCx+Rue6Hkwoun8h1k= Received: from arinc9-PC.lan (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 1663508507395778.7535002580399; Sun, 18 Sep 2022 06:41:47 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Krzysztof Kozlowski , Rob Herring , Matthias Brugger , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Thomas Bogendoerfer , Greg Kroah-Hartman , Sean Wang , Landen Chao , DENG Qingfang , Sergio Paracuellos , erkin.bozoglu@xeront.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, =?utf-8?b?QXI=?= =?utf-8?b?xLFuw6cgw5xOQUw=?= , Rob Herring Subject: [PATCH v3 net-next 03/10] dt-bindings: net: dsa: mediatek,mt7530: expand gpio-controller description Date: Sun, 18 Sep 2022 16:41:11 +0300 Message-Id: <20220918134118.554813-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220918134118.554813-1-arinc.unal@arinc9.com> References: <20220918134118.554813-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Expand the description of the gpio-controller property to include the controllable pins of the MT7530 switch. The gpio-controller property is only used for the MT7530 switch. Therefore, invalidate it for the MT7531 switch. Signed-off-by: Arınç ÜNAL Acked-by: Rob Herring --- .../devicetree/bindings/net/dsa/mediatek,mt7530.yaml | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 2c73d13adf14..3ec4fffec780 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -104,7 +104,14 @@ properties: gpio-controller: type: boolean description: - If defined, MT7530's LED controller will run on GPIO mode. + If defined, LED controller of the MT7530 switch will run on GPIO mode. + + There are 15 controllable pins. + port 0 LED 0..2 as GPIO 0..2 + port 1 LED 0..2 as GPIO 3..5 + port 2 LED 0..2 as GPIO 6..8 + port 3 LED 0..2 as GPIO 9..11 + port 4 LED 0..2 as GPIO 12..14 "#interrupt-cells": const: 1 @@ -272,6 +279,7 @@ allOf: then: $ref: "#/$defs/mt7531-dsa-port" properties: + gpio-controller: false mediatek,mcm: false - if: From patchwork Sun Sep 18 13:41:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 1679023 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=arinc9.com header.i=arinc.unal@arinc9.com header.a=rsa-sha256 header.s=zmail header.b=XZskVF4J; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4MVps13hR4z1ync for ; Sun, 18 Sep 2022 23:42:29 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229728AbiIRNmX (ORCPT ); Sun, 18 Sep 2022 09:42:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229698AbiIRNmR (ORCPT ); Sun, 18 Sep 2022 09:42:17 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC6E01A398; Sun, 18 Sep 2022 06:42:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1663508514; cv=none; d=zohomail.com; s=zohoarc; b=S1qAyiqCwwGXSXSaum2foeUyBtDGDSP6pgA0t5noF79kSnhl/lmGngF72rFn90F3lN+zVir7kHfxNzCiYKBL1FDiyro3KtOW36MEUY5FJ0zzD3vn1ffdrXPDUxAxXo3/0q/JTgZwy3/03D4kTe8gPNXAXHZazI3UIKFFDZyAJw8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1663508514; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=QOwUQUGXzXW7a2cfxQ09efax8bzqXaZd89GFxaHq3Yo=; b=fkPnYbKyc3pHI+tKoFCQd1zRoEO3frde32u0NbrU/Dr+t6jUBIqIkIwUGN/7MF43eYuGwD8hlYQ8eBHzWJma/6NnIVlMr9xoEwxIyXcoFHL2l4zwTCFY7QJC/M4FLrzSVB2tVxwoJS0kmCmGTur0vx3ZHSk4GYRYoacNcTwH0Oc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1663508514; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=QOwUQUGXzXW7a2cfxQ09efax8bzqXaZd89GFxaHq3Yo=; b=XZskVF4Jmr/dR96L5mac1dJRQIGQGMg3pfnfMOKRs71CoFYrmoH7AsSVlQJH/a/5 KUTFhFOyprMER/LJvT6uYLBs+4N7hAeDwy1ZzUuvms46xHUP9bLwKg6QqLuCnHCcLEP OxBu5HYttglL5R106jmLgC6K0ErccISSrzy9lzCc= Received: from arinc9-PC.lan (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 1663508513207144.86270917599222; Sun, 18 Sep 2022 06:41:53 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Krzysztof Kozlowski , Rob Herring , Matthias Brugger , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Thomas Bogendoerfer , Greg Kroah-Hartman , Sean Wang , Landen Chao , DENG Qingfang , Sergio Paracuellos , erkin.bozoglu@xeront.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, =?utf-8?b?QXI=?= =?utf-8?b?xLFuw6cgw5xOQUw=?= Subject: [PATCH v3 net-next 04/10] dt-bindings: memory: mt7621: add syscon as compatible string Date: Sun, 18 Sep 2022 16:41:12 +0300 Message-Id: <20220918134118.554813-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220918134118.554813-1-arinc.unal@arinc9.com> References: <20220918134118.554813-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The syscon string was introduced because the mt7621 clock driver needs to read some registers creating a regmap from the syscon. The bindings were added before the clock driver was properly mainlined and at first the clock driver was using ralink architecture dependent operations rt_memc_* defined in 'arch/mips/include/asm/mach-ralink/ralink_regs.h'. This string is already there on the memory controller node on mt7621.dtsi. Add syscon as a constant string on the compatible property, now that memc became a syscon. Update the example accordingly. Fixes: 5278e4a181ff ("dt-bindings: memory: add binding for Mediatek's MT7621 SDRAM memory controller") Signed-off-by: Arınç ÜNAL Acked-by: Sergio Paracuellos --- .../bindings/memory-controllers/mediatek,mt7621-memc.yaml | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml index 85e02854f083..ba8cd6d81d08 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml @@ -11,7 +11,9 @@ maintainers: properties: compatible: - const: mediatek,mt7621-memc + items: + - const: mediatek,mt7621-memc + - const: syscon reg: maxItems: 1 @@ -24,7 +26,7 @@ additionalProperties: false examples: - | - memory-controller@5000 { - compatible = "mediatek,mt7621-memc"; + syscon@5000 { + compatible = "mediatek,mt7621-memc", "syscon"; reg = <0x5000 0x1000>; };