From patchwork Mon Sep 12 01:47:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chong, Teik Heng" X-Patchwork-Id: 1676936 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Y2t4ryyK; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MR5C31fYRz1ynm for ; Mon, 12 Sep 2022 22:15:11 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 10E9F84B93; Mon, 12 Sep 2022 14:14:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Y2t4ryyK"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 179B3845EF; Mon, 12 Sep 2022 03:48:11 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1B4D181F4E for ; Mon, 12 Sep 2022 03:48:05 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=teik.heng.chong@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662947286; x=1694483286; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=9/Nx41a0ac3gOSa4qTi1cTyI9uNneWr46nw1bjwT9y8=; b=Y2t4ryyK8Q7VcC5Hp4jk03AAZSExT3U4KzrKK2vEwH5WRinp1RDaGFBP Ef8WPXhfxjOassh8gE59tx4kESftBnu9lfbivM7j7Pzhv3ZOvzdifPcKa fO4uTiWOoK2qez36XB96zd8VWrC3tPvJOiLbcCi9JD1NnEqzHftrHDA6p lL9OrTpNlovBG3zHsO6L20XqQZIi4LM4JIAqkSN5nQNJalZwk3aAk6g5N UlKbmv4Tj4XI9iYHNhSycjfSbfIs7PAdsXgxk5Y/nq3vMp5p05wLjVcW7 ZLT+kSfgPB3KbbwALE5XodIHMiU4NN7fTQPmQneHUEFR2VAjqO2MCNFEk A==; X-IronPort-AV: E=McAfee;i="6500,9779,10467"; a="299107875" X-IronPort-AV: E=Sophos;i="5.93,308,1654585200"; d="scan'208";a="299107875" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2022 18:48:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,308,1654585200"; d="scan'208";a="944445389" Received: from pgli4336.png.intel.com ([10.221.172.41]) by fmsmga005.fm.intel.com with ESMTP; 11 Sep 2022 18:48:00 -0700 From: teik.heng.chong@intel.com To: u-boot@lists.denx.de Cc: Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Hazim , Jit Loon Lim , Sieu Mun Tang , Teik Heng Chong Subject: [PATCH] ddr: socfpga: Add ECC DRAM scrubbing support for gen5 Date: Mon, 12 Sep 2022 09:47:36 +0800 Message-Id: <20220912014736.20824-1-teik.heng.chong@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-Mailman-Approved-At: Mon, 12 Sep 2022 14:14:41 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee The SDRAM must first be rewritten by zeroes if ECC is used to initialize the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a case. This scrubbing implementation turns the caches on temporarily, then overwrites the whole RAM with zeroes, flushes the caches and turns them off again. This provides satisfactory performance. Signed-off-by: Tien Fong Chee Signed-off-by: Teik Heng Chong --- arch/arm/mach-socfpga/spl_gen5.c | 4 +++ drivers/ddr/altera/sdram_gen5.c | 57 ++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 287fbd1713..b79d8cbd5d 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -29,6 +29,8 @@ DECLARE_GLOBAL_DATA_PTR; +static struct bd_info bdata __section(".data"); + u32 spl_boot_device(void) { const u32 bsel = readl(socfpga_get_sysmgr_addr() + @@ -148,6 +150,8 @@ void board_init_f(ulong dummy) /* enable console uart printing */ preloader_console_init(); + gd->bd = &bdata; + ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c index 8d3ce495de..9d69f009e9 100644 --- a/drivers/ddr/altera/sdram_gen5.c +++ b/drivers/ddr/altera/sdram_gen5.c @@ -3,6 +3,7 @@ * Copyright Altera Corporation (C) 2014-2015 */ #include +#include #include #include #include @@ -17,10 +18,14 @@ #include #include #include +#include #include +#include #include "sequencer.h" +#define PGTABLE_OFF 0x4000 + #ifdef CONFIG_SPL_BUILD struct altera_gen5_sdram_priv { @@ -563,6 +568,54 @@ static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl) return temp; } +static int sdram_is_ecc_enabled(struct socfpga_sdr_ctrl *sdr_ctrl) +{ + return !!(readl(&sdr_ctrl->ctrl_cfg) & + SDR_CTRLGRP_CTRLCFG_ECCEN_MASK); +} + +/* Initialize SDRAM ECC bits to avoid false DBE */ +static void sdram_init_ecc_bits(phys_size_t size) +{ + phys_size_t start, size_init, start_addr; + + start = get_timer(0); + + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = size; + + gd->arch.tlb_addr = gd->bd->bi_dram[0].start + PGTABLE_OFF; + gd->arch.tlb_size = PGTABLE_SIZE; + + memset((void *)gd->bd->bi_dram[0].start, 0, gd->arch.tlb_addr + + gd->arch.tlb_size); + + icache_enable(); + dcache_enable(); + + printf("DDRCAL: Scrubbing ECC RAM (%lu MiB).\n", size >> 20); + + start_addr = gd->arch.tlb_addr + gd->arch.tlb_size; + size -= (gd->arch.tlb_addr + gd->arch.tlb_size); + + while (size > 0) { + size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size); + memset((void *)start_addr, 0, size_init); + size -= size_init; + start_addr += size_init; + WATCHDOG_RESET(); + } + + flush_dcache_all(); + + printf("DDRCAL: Scrubbing ECC RAM done.\n"); + + dcache_disable(); + + printf("DDRCAL: SDRAM-ECC initialized success with %d ms\n", + (u32)get_timer(start)); +} + static int altera_gen5_sdram_of_to_plat(struct udevice *dev) { struct altera_gen5_sdram_plat *plat = dev_get_plat(dev); @@ -605,6 +658,10 @@ static int altera_gen5_sdram_probe(struct udevice *dev) sdram_size = sdram_calculate_size(sdr_ctrl); debug("SDRAM: %ld MiB\n", sdram_size >> 20); + if (sdram_is_ecc_enabled(sdr_ctrl)) { + sdram_init_ecc_bits(sdram_size); + } + /* Sanity check ensure correct SDRAM size specified */ if (get_ram_size(0, sdram_size) != sdram_size) { puts("SDRAM size check failed!\n");