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Tue, 30 Aug 2022 10:48:35 -0700 (PDT) Received: from vineetg-framework.hq.rivosinc.com ([12.3.194.138]) by smtp.gmail.com with ESMTPSA id w5-20020aa79545000000b005386162bc2asm3618852pfq.92.2022.08.30.10.48.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 10:48:34 -0700 (PDT) From: Vineet Gupta To: gcc-patches@gcc.gnu.org Subject: [PATCH 1/2] RISC-V: remove deprecate pic code model macro Date: Tue, 30 Aug 2022 10:48:29 -0700 Message-Id: <20220830174830.224541-2-vineetg@rivosinc.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220830174830.224541-1-vineetg@rivosinc.com> References: <20220830174830.224541-1-vineetg@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: collison@rivosinc.com, gnu-toolchain@rivosinc.com, Vineet Gupta , kito.cheng@gmail.com, Philipp Tomsich Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Came across this deprecated symbol when looking around for -mexplicit-relocs handling in code Signed-off-by: Vineet Gupta --- gcc/config/riscv/riscv-c.cc | 3 --- 1 file changed, 3 deletions(-) diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index eb7ef09297e9..bba72cf77a82 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -93,9 +93,6 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) break; case CM_PIC: - /* __riscv_cmodel_pic is deprecated, and will removed in next GCC release. - see https://github.com/riscv/riscv-c-api-doc/pull/11 */ - builtin_define ("__riscv_cmodel_pic"); /* FALLTHROUGH. */ case CM_MEDANY: From patchwork Tue Aug 30 17:48:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 1671984 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=rivosinc-com.20210112.gappssmtp.com header.i=@rivosinc-com.20210112.gappssmtp.com header.a=rsa-sha256 header.s=20210112 header.b=w6jyMmYq; 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Removing it might potentially affect USE_LOAD_ADDRESS_MACRO() but seems unlikely. Signed-off-by: Vineet Gupta --- gcc/config/riscv/riscv-c.cc | 4 ---- gcc/config/riscv/riscv-opts.h | 3 +-- gcc/config/riscv/riscv.cc | 2 +- 3 files changed, 2 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index bba72cf77a82..7064fcf142fe 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -92,13 +92,9 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) builtin_define ("__riscv_cmodel_medlow"); break; - case CM_PIC: - /* FALLTHROUGH. */ - case CM_MEDANY: builtin_define ("__riscv_cmodel_medany"); break; - } if (TARGET_MIN_VLEN != 0) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 85e869e62e3a..ce3237beca7a 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -34,8 +34,7 @@ extern enum riscv_abi_type riscv_abi; enum riscv_code_model { CM_MEDLOW, - CM_MEDANY, - CM_PIC + CM_MEDANY }; extern enum riscv_code_model riscv_cmodel; diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 7c120eaa8e33..a239fe43047c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5162,7 +5162,7 @@ riscv_option_override (void) init_machine_status = &riscv_init_machine_status; if (flag_pic) - riscv_cmodel = CM_PIC; + riscv_cmodel = CM_MEDANY; /* We get better code with explicit relocs for CM_MEDLOW, but worse code for the others (for now). Pick the best default. */