From patchwork Wed Aug 17 09:06:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Oberfichtner X-Patchwork-Id: 1667177 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=mT+yQB/b; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4M72FP5Ldsz1ygF for ; Wed, 17 Aug 2022 19:06:33 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9033C849D2; Wed, 17 Aug 2022 11:06:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1660727188; bh=7zVfOf5o8jhCa77s5fekS0dH6roU4NltsOf6W76gmZc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=mT+yQB/b3dFAL/QR3wiLh19lrLUup9oBbRdRNc+5GEhnGI+/y+olCk0OEcd3S6rtg k5rhyB/t4lMq2YYSTssl9qSOZBkYExE7Kx4cHDt129TDyhf18Ukey1gDqzpaO7CLYH CiB30QrI437yS6xc9ckD2FOtG1XPwYj2w0lCEGVEYIRTmw9vllrMwOnBF+cafzKLtz GR0j8kCe7+kdW0QvV6wkD6rNIrWUMHFFw+yKhp+Jz1cC2P1dgN1SNl1pfNLp+WeYV5 m75RVzbfSziTWBS5L+k/VzMvulmJXHJxp7AUB+jEKAg8yYP/ZIPjDmCoj53XwCBgrk oEJPgWOdAwHGA== Received: by phobos.denx.de (Postfix, from userid 109) id D1FA6849B8; Wed, 17 Aug 2022 11:06:26 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.3 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,SPF_NEUTRAL,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.2 Received: from xpert.denx.de (unknown [62.91.23.180]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8AC11849B8 for ; Wed, 17 Aug 2022 11:06:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=pro@denx.de Received: by xpert.denx.de (Postfix, from userid 535) id 3BA093E06F3; Wed, 17 Aug 2022 11:06:23 +0200 (CEST) From: Philip Oberfichtner To: u-boot@lists.denx.de Cc: Stefano Babic , Marek Vasut , Christoph Niedermaier , Philip Oberfichtner , Anatolij Gustschin , Bharat Gooty , Chin-Liang See , Dalon Westergreen , Dinh Nguyen , Holger Brunck , Humberto Naves , Jaehoon Chung , Jim Liu , =?utf-8?q?Marek_Beh=C3=BAn?= , Michal Simek , Nikita Kiryanov , Patrick Delaunay , Pavel Machek , =?utf-8?q?Pawe=C5=82_Anikiel?= , Peng Fan , Rayagonda Kokatanur , Rick Chen , Rui Miguel Silva , Simon Glass , Stanley Chu , Stefan Roese , Stephan Gerhold , Thomas Huth , Wolfgang Grandegger , Wolfgang Wallner Subject: [PATCH v4 1/3] Convert CONFIG_SYS_L2_PL310 to Kconfig Date: Wed, 17 Aug 2022 11:06:09 +0200 Message-Id: <20220817090611.3292993-2-pro@denx.de> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220817090611.3292993-1-pro@denx.de> References: <20220817090611.3292993-1-pro@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean This converts CONFIG_SYS_L2_PL310 to Kconfig. For omap2 and mvebu the 'select SYS_L2_PL310' locations were determined using ./tools/moveconfig -i CONFIG_SYS_L2_PL310. For mx6 I manually chose ARCH_MX6 as 'select' location. The correctness has been verified using $ ./tools/moveconfig.py -f ARCH_MX6 ~SYS_L2_PL310 ~SYS_L2CACHE_OFF 0 matches That means whenever an ARCH_MX6 board had SYS_L2_PL310 disabled, this was correctly reflected in SYS_L2CACHE_OFF. Thus it's safe to insert the 'select' statement under ARCH_MX6. Signed-off-by: Philip Oberfichtner --- I wonder if we could further reduce the diffstat by using 'select' for all the socfpga boards. I did not find an appropriate way - I'm open for suggestions, though. Changes in v4: - Reduce diffstat by using 'select' statements for omap2, mvebu and mx6 based boards Changes in v3: new README | 2 -- arch/arm/Kconfig | 5 +++++ arch/arm/mach-mvebu/Kconfig | 1 + arch/arm/mach-mvebu/include/mach/config.h | 2 -- arch/arm/mach-omap2/Kconfig | 1 + configs/omap4_panda_defconfig | 1 + configs/omap4_sdp4430_defconfig | 1 + configs/poleg_evb_defconfig | 1 + configs/socfpga_arria10_defconfig | 1 + configs/socfpga_arria5_defconfig | 1 + configs/socfpga_chameleonv3_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_dbm_soc1_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_de10_standard_defconfig | 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_is1_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_secu1_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + configs/stemmy_defconfig | 1 + include/configs/am43xx_evm.h | 1 - include/configs/brppt2.h | 1 - include/configs/cm_t43.h | 1 - include/configs/mx6_common.h | 1 - include/configs/odroid.h | 1 - include/configs/poleg.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/stemmy.h | 1 - include/configs/ti_omap4_common.h | 1 - include/configs/trats.h | 1 - include/configs/trats2.h | 1 - include/configs/zynq-common.h | 1 - scripts/config_whitelist.txt | 1 - 38 files changed, 27 insertions(+), 17 deletions(-) diff --git a/README b/README index 6b6f722733..595f007aaf 100644 --- a/README +++ b/README @@ -496,8 +496,6 @@ The following options need to be configured: the defaults discussed just above. - Cache Configuration for ARM: - CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache - controller CONFIG_SYS_PL310_BASE - Physical base address of PL310 controller register space diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 949ebb46ba..b094d2d51f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -488,6 +488,10 @@ config TPL_SYS_THUMB_BUILD density. For ARM architectures that support Thumb2 this flag will result in Thumb2 code generated by GCC. +config SYS_L2_PL310 + bool "ARM PL310 L2 cache controller" + help + Enable support for ARM PL310 L2 cache controller in U-Boot config SYS_L2CACHE_OFF bool "L2cache off" @@ -989,6 +993,7 @@ config ARCH_MX6 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE + select SYS_L2_PL310 if !SYS_L2CACHE_OFF imply MXC_GPIO imply SYS_THUMB_BUILD imply SPL_SEPARATE_BSS diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index a81b8e2b0d..2ebe341ed1 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -14,6 +14,7 @@ config ARMADA_32BIT select SPL_SKIP_LOWLEVEL_INIT if SPL select SPL_SIMPLE_BUS if SPL select SUPPORT_SPL + select SYS_L2_PL310 if !SYS_L2CACHE_OFF select TRANSLATION_OFFSET select SPL_SYS_NO_VECTOR_TABLE if SPL select ARCH_VERY_EARLY_INIT diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 4add0d9e10..0bba0a4cf9 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -25,8 +25,6 @@ #define MV88F78X60 /* for the DDR training bin_hdr code */ #endif -#define CONFIG_SYS_L2_PL310 - #define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE /* Needed for SPI NOR booting in SPL */ diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index fa41047476..fee437c4dc 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -96,6 +96,7 @@ config TI816X config AM43XX bool "AM43XX SoC" select SPECIFY_CONSOLE_INDEX + select SYS_L2_PL310 if !SYS_L2CACHE_OFF imply NAND_OMAP_ELM imply NAND_OMAP_GPMC imply SPL_DM diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig index bd6c2ce4ca..899ba50a16 100644 --- a/configs/omap4_panda_defconfig +++ b/configs/omap4_panda_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_DEFAULT_DEVICE_TREE="omap4-panda" diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig index 62eb75d1f9..82cfc4ab1a 100644 --- a/configs/omap4_sdp4430_defconfig +++ b/configs/omap4_sdp4430_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_OMAP2PLUS=y diff --git a/configs/poleg_evb_defconfig b/configs/poleg_evb_defconfig index 16f6215148..4669c7fe86 100644 --- a/configs/poleg_evb_defconfig +++ b/configs/poleg_evb_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_NPCM=y CONFIG_SYS_TEXT_BASE=0x8200 CONFIG_SYS_MALLOC_LEN=0x240000 diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index c98c106851..716a68a67b 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 24c21090b1..810604ec03 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig index e78d3b51de..80a965c7e2 100644 --- a/configs/socfpga_chameleonv3_defconfig +++ b/configs/socfpga_chameleonv3_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x4400 diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index d010b54240..7383fa1d3e 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index a1574b6a5d..9f1bed2b75 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index ec7355d2cc..8e4154f46c 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index b62f029962..713048ab3a 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_de10_standard_defconfig b/configs/socfpga_de10_standard_defconfig index b8bc9da4d0..67b2bafbe8 100644 --- a/configs/socfpga_de10_standard_defconfig +++ b/configs/socfpga_de10_standard_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 749ec540b4..8bae98e130 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 958adfe25a..b7735689bc 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 18e125f5bd..0e47bcd4e7 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index 83e24402a8..89df845ad7 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x800 diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 2a02f1dbfa..c16b3e4820 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 3d0c48d766..7bcea6726b 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x2000 diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index def2ee8dbc..55388da88c 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x4000 diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index d0c87416ef..9c89d631f5 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x4000 diff --git a/configs/stemmy_defconfig b/configs/stemmy_defconfig index 7fc0a39872..f1d3ef5b12 100644 --- a/configs/stemmy_defconfig +++ b/configs/stemmy_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_L2_PL310=y CONFIG_ARCH_U8500=y CONFIG_SUPPORT_PASSING_ATAGS=y # CONFIG_SETUP_MEMORY_TAGS is not set diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 87d3a27099..fc82a8c003 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -29,7 +29,6 @@ /* SPL defines. */ /* Enabling L2 Cache */ -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x48242000 /* diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index adaba410ce..0c7fe5f3ab 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -13,7 +13,6 @@ /* -- i.mx6 specifica -- */ #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE L2_PL310_BASE #endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 07c5cb8ded..50cb2a4718 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -36,7 +36,6 @@ #define CONFIG_POWER_TPS65218 /* Enabling L2 Cache */ -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x48242000 /* diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index e416f81e43..4314556754 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -12,7 +12,6 @@ #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ #else #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE L2_PL310_BASE #endif diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 7448cc9520..babd3ca963 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -14,7 +14,6 @@ #include #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x10502000 #endif diff --git a/include/configs/poleg.h b/include/configs/poleg.h index f1c259f476..05253d59ef 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -7,7 +7,6 @@ #define __CONFIG_POLEG_H #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 1 #define CONFIG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/ #endif diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 4a7da76e51..c3f30afe2b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -48,7 +48,6 @@ /* * Cache */ -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h index 71b25c23b1..3c70856fc7 100644 --- a/include/configs/stemmy.h +++ b/include/configs/stemmy.h @@ -15,7 +15,6 @@ */ /* FIXME: This should be loaded from device tree... */ -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0xa0412000 /* Linux does not boot if FDT / initrd is loaded to end of RAM */ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 3d78972bfe..0568946fc8 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -12,7 +12,6 @@ #define __CONFIG_TI_OMAP4_COMMON_H #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 1 #define CONFIG_SYS_PL310_BASE 0x48242000 #endif diff --git a/include/configs/trats.h b/include/configs/trats.h index 53f5a6996b..530b413d5b 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -12,7 +12,6 @@ #include #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x10502000 #endif diff --git a/include/configs/trats2.h b/include/configs/trats2.h index b7449dab8b..06c1fcd23e 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -13,7 +13,6 @@ #include #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x10502000 #endif diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 75ae68766f..dc0cba0010 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -11,7 +11,6 @@ /* Cache options */ #ifndef CONFIG_SYS_L2CACHE_OFF -# define CONFIG_SYS_L2_PL310 # define CONFIG_SYS_PL310_BASE 0xf8f02000 #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 4f628e0f10..d9d24c0ae0 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -908,7 +908,6 @@ CONFIG_SYS_JFFS2_FIRST_SECTOR CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_KMBEC_FPGA_BASE CONFIG_SYS_KMBEC_FPGA_SIZE -CONFIG_SYS_L2_PL310 CONFIG_SYS_L2_SIZE CONFIG_SYS_L3_SIZE CONFIG_SYS_LATCH_ADDR From patchwork Wed Aug 17 09:06:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Oberfichtner X-Patchwork-Id: 1667178 X-Patchwork-Delegate: trini@ti.com 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SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.3 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,SPF_NEUTRAL,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.2 Received: from xpert.denx.de (unknown [62.91.23.180]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 72D0684995 for ; Wed, 17 Aug 2022 11:06:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=pro@denx.de Received: by xpert.denx.de (Postfix, from userid 535) id 3A16A3E06F3; Wed, 17 Aug 2022 11:06:34 +0200 (CEST) From: Philip Oberfichtner To: u-boot@lists.denx.de Cc: Stefano Babic , Marek Vasut , Christoph Niedermaier , Philip Oberfichtner , Bharat Gooty , Dzmitry Sankouski , Rayagonda Kokatanur , Sean Anderson , Stefan Roese , Tom Rini Subject: [PATCH v4 2/3] ARM: cache: Allow SPL to build cache-pl310.c Date: Wed, 17 Aug 2022 11:06:10 +0200 Message-Id: <20220817090611.3292993-3-pro@denx.de> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220817090611.3292993-1-pro@denx.de> References: <20220817090611.3292993-1-pro@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Introduce the new Kconfig symbol CONFIG_SPL_SYS_L2_PL310 to allow the SPL to build cache-pl310.c. Before this commit, the SPL could enable the PL310 L2 cache [1], but the cache maintenance functions from cache-pl310.c were only useable for non-SPL builds. After enabling the cache one must be able to flush it, too. Thus this commit allows cache-pl310.c to be included in the SPL build. [1] See for example arch/arm/mach-imx/cache.c: v7_outer_cache_enable() Signed-off-by: Philip Oberfichtner --- (no changes since v3) Changes in v3: - Introduce CONFIG_SPL_SYS_L2_PL310 arch/arm/Kconfig | 5 +++++ arch/arm/lib/Makefile | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b094d2d51f..318e5e82ea 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -493,6 +493,11 @@ config SYS_L2_PL310 help Enable support for ARM PL310 L2 cache controller in U-Boot +config SPL_SYS_L2_PL310 + bool "ARM PL310 L2 cache controller in SPL" + help + Enable support for ARM PL310 L2 cache controller in SPL + config SYS_L2CACHE_OFF bool "L2cache off" help diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index c603fe61bc..d137b4bf0f 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -33,7 +33,6 @@ obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o -obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o else obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o @@ -46,6 +45,7 @@ else obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o endif +obj-$(CONFIG_$(SPL_TPL_)SYS_L2_PL310) += cache-pl310.o obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o ifneq ($(filter y,$(CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR) $(CONFIG_SAVE_PREV_BL_FDT_ADDR)),) From patchwork Wed Aug 17 09:06:11 2022 Content-Type: text/plain; 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Wed, 17 Aug 2022 11:06:39 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.3 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,SPF_NEUTRAL,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.2 Received: from xpert.denx.de (unknown [62.91.23.180]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D44A8849F3 for ; Wed, 17 Aug 2022 11:06:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=pro@denx.de Received: by xpert.denx.de (Postfix, from userid 535) id 9082E3E06F3; Wed, 17 Aug 2022 11:06:36 +0200 (CEST) From: Philip Oberfichtner To: u-boot@lists.denx.de Cc: Stefano Babic , Marek Vasut , Christoph Niedermaier , Philip Oberfichtner , Andreas Geisreiter , Tom Rini , u-boot@dh-electronics.com Subject: [PATCH v4 3/3] ARM: imx6: dh-imx6: Enable d-cache early in SPL Date: Wed, 17 Aug 2022 11:06:11 +0200 Message-Id: <20220817090611.3292993-4-pro@denx.de> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220817090611.3292993-1-pro@denx.de> References: <20220817090611.3292993-1-pro@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Marek Vasut Enable d-cache early in SPL right after DRAM is started up. This reduces U-Boot proper load time by 650ms when loaded from SPI NOR. Signed-off-by: Marek Vasut Signed-off-by: Philip Oberfichtner --- Changes in v4: - Elaborate on dcache_disable() comment Changes in v3: - Use newly introduced Kconfig symbol for dh_imx6_defconfig Changes in v2: - Add comment to explain the relevance of dcache_disable() board/dhelectronics/dh_imx6/dh_imx6_spl.c | 32 +++++++++++++++++++++++ configs/dh_imx6_defconfig | 1 + 2 files changed, 33 insertions(+) diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index e49e97724a..580b98811c 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -14,11 +15,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -610,6 +613,20 @@ static void dhcom_spl_dram_init(void) } } +void dram_bank_mmu_setup(int bank) +{ + int i; + + set_section_dcache(ROMCP_ARB_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION); + set_section_dcache(IRAM_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION); + + for (i = MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT; + i < ((MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT) + + (SZ_1G >> MMU_SECTION_SHIFT)); + i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); +} + void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ @@ -636,9 +653,24 @@ void board_init_f(ulong dummy) /* DDR3 initialization */ dhcom_spl_dram_init(); + /* Set up early MMU tables at the beginning of DRAM and start d-cache */ + gd->arch.tlb_addr = MMDC0_ARB_BASE_ADDR + SZ_32M; + gd->arch.tlb_size = PGTABLE_SIZE; + enable_caches(); + /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); } + +void spl_board_prepare_for_boot(void) +{ + /* + * Flush dcache. Without it U-Boot proper would hang at random locations. Presumably this is + * due to dirty cache lines remaining after SPL passes control. When U-Boot proper later on + * calls invalidate_dcache_all(), those dirty cache lines will get lost. + */ + dcache_disable(); +} diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 051816f719..1be6ae62ce 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SPL_SYS_L2_PL310=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SYS_MALLOC_F_LEN=0x1000