From patchwork Wed Jul 20 15:39:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xavier Drudis Ferran X-Patchwork-Id: 1658707 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Lp0Hp12blz9sFr for ; Thu, 21 Jul 2022 01:39:34 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 74A9784079; Wed, 20 Jul 2022 17:39:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinet.cat Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id EE40C82EEA; Wed, 20 Jul 2022 17:39:26 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mx1.tinet.cat (mx1.dipta.cat [195.76.233.59]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id CA1D280E94 for ; Wed, 20 Jul 2022 17:39:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinet.cat Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=xdrudis@tinet.cat X-ASG-Debug-ID: 1658331562-12aaf258c3a79a80001-4l7tJC Received: from smtp01.tinet.cat (smtp01.tinet.org [195.77.216.131]) by mx1.tinet.cat with ESMTP id IhSq4xYaNG9mWPoY; Wed, 20 Jul 2022 17:39:22 +0200 (CEST) X-Barracuda-Envelope-From: xdrudis@tinet.cat X-Barracuda-Effective-Source-IP: smtp01.tinet.org[195.77.216.131] X-Barracuda-Apparent-Source-IP: 195.77.216.131 Received: from begut (99.red-79-152-185.dynamicip.rima-tde.net [79.152.185.99]) by smtp01.tinet.cat (Postfix) with ESMTPSA id AD0AF605E0C3; Wed, 20 Jul 2022 17:39:22 +0200 (CEST) Date: Wed, 20 Jul 2022 17:39:21 +0200 From: Xavier Drudis Ferran To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R Subject: [PATCH v3 1/4] mtd: spi: spi-nor: Add Rock pi 4b new flash chip Message-ID: <20220720153921.GE2049@begut> X-ASG-Orig-Subj: [PATCH v3 1/4] mtd: spi: spi-nor: Add Rock pi 4b new flash chip References: <20220720153610.GD2049@begut> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220720153610.GD2049@begut> User-Agent: Mutt/1.10.1 (2018-07-13) X-Barracuda-Connect: smtp01.tinet.org[195.77.216.131] X-Barracuda-Start-Time: 1658331562 X-Barracuda-URL: https://webmail.tinet.cat:443/cgi-mod/mark.cgi X-Barracuda-Scan-Msg-Size: 2070 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.5015 1.0000 0.7500 X-Barracuda-Spam-Score: 1.25 X-Barracuda-Spam-Status: No, SCORE=1.25 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=6.0 KILL_LEVEL=8.0 tests=BSF_RULE7568M X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.99510 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- 0.50 BSF_RULE7568M Custom Rule 7568M X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Radxa Rock Pi 4B from version 1.4 on carries a 4MiB XTX Technology Inc 25F32B SPI NOR Flash. (previous versions had pads where users could solder different chips). Add its parameters to spi-nor-ids.c so U-Boot can discover it and (after further changes) we can boot from SPI. Note that the Flash is declared to be dual and quad capable because the datasheet [4] says so but I couldn't try it because in Rock Pi 4 it is not wired for QuadSPI, and rk3399 does not seem to support dual SPI either (or I couldn't find any register to configure spi1tx and spi1rx as bidirectional). But the same Flash part could be used as in quad or dual model in some other board. Likewise locks are in the datasheet but untested. The part has been added to downstream U-Boot [1] and linux [2] [3]: Changed from v2: - no change Changed from v1: - no change Link: [1] https://github.com/armbian/build/commit/c41cb4c454570127ad3238f6b901fbf3aa773c Link: [2] https://github.com/radxa/kernel/blob/release-4.4-rockpi4/drivers/mtd/spi-nor/spi-nor.c Link: [3] https://github.com/radxa/kernel/commit/8216f17965de7bc7ced7092aab0e2bfe16838a4 Link: [4] https://www.xtxtech.com/download/?AId=157 Signed-off-by: Xavier Drudis Ferran Cc: Jagan Teki Cc: Vignesh R --- drivers/mtd/spi/spi-nor-ids.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4fe8b0d92c..b09df00bab 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -452,6 +452,9 @@ const struct flash_info spi_nor_ids[] = { #ifdef CONFIG_SPI_FLASH_XTX /* XTX Technology (Shenzhen) Limited */ { INFO("xt25f128b", 0x0b4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("xt25f32b", 0x0b4016, 0, 64 * 1024, 64, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ + | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_SST26LOCK) }, #endif { }, }; From patchwork Wed Jul 20 15:41:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xavier Drudis Ferran X-Patchwork-Id: 1658708 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Lp0LW70Mmz9sFr for ; Thu, 21 Jul 2022 01:41:55 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4DA4F810EA; Wed, 20 Jul 2022 17:41:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinet.cat Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 7FA5482EEA; Wed, 20 Jul 2022 17:41:48 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mx1.tinet.cat (mx1.dipta.cat [195.76.233.59]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E0D1C80E94 for ; Wed, 20 Jul 2022 17:41:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tinet.cat Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=xdrudis@tinet.cat X-ASG-Debug-ID: 1658331704-12aaf258c3a79f10001-4l7tJC Received: from smtp01.tinet.cat (smtp01.tinet.cat [195.77.216.131]) by mx1.tinet.cat with ESMTP id UXr2JIQ97TFSWApY; Wed, 20 Jul 2022 17:41:44 +0200 (CEST) X-Barracuda-Envelope-From: xdrudis@tinet.cat X-Barracuda-Effective-Source-IP: smtp01.tinet.cat[195.77.216.131] X-Barracuda-Apparent-Source-IP: 195.77.216.131 Received: from begut (99.red-79-152-185.dynamicip.rima-tde.net [79.152.185.99]) by smtp01.tinet.cat (Postfix) with ESMTPSA id BBFF5605E0C5; Wed, 20 Jul 2022 17:41:44 +0200 (CEST) Date: Wed, 20 Jul 2022 17:41:43 +0200 From: Xavier Drudis Ferran To: u-boot@lists.denx.de Cc: Simon Glass , Philipp Tomsich , Kever Yang Subject: [PATCH v3 2/4] rockchip: rk-3399: rock-pi-4: dts: Add XTX SPI NOR 4MiB Flash chip in Rock Pi 4 boards from rev 1.4 on. Message-ID: <20220720154142.GF2049@begut> X-ASG-Orig-Subj: [PATCH v3 2/4] rockchip: rk-3399: rock-pi-4: dts: Add XTX SPI NOR 4MiB Flash chip in Rock Pi 4 boards from rev 1.4 on. References: <20220720153610.GD2049@begut> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220720153610.GD2049@begut> User-Agent: Mutt/1.10.1 (2018-07-13) X-Barracuda-Connect: smtp01.tinet.cat[195.77.216.131] X-Barracuda-Start-Time: 1658331704 X-Barracuda-URL: https://webmail.tinet.cat:443/cgi-mod/mark.cgi X-Barracuda-Scan-Msg-Size: 4346 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: SPAM GLOBAL 0.9129 1.0000 3.3642 X-Barracuda-Spam-Score: 3.36 X-Barracuda-Spam-Status: No, SCORE=3.36 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=6.0 KILL_LEVEL=8.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.99510 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Configure Rock Pi 4 to boot from SPI NOR Flash. Based on flash chip, board documentation and tests, this is the fastest I could use it. This seems to be the minimum necessary configuration for Rock Pi 4 to be able to boot from SPI NOR Flash. With the next patch, it works to sf probe 1:0, sf read, sf erase, sf write, sf read and then boot linux and flashrom can write to it. Sometimes flashrom seems to fail to write when at U-Boot stage there was no sf read or write, not sure why. Might work better after a little while off power. Note: It seems to work with or without CONFIG_SPL_SPI_FLASH_TINY If I disable it, and enable CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT I have to increase CONFIG_SPL_MAX_SIZE (I set it to 0x2e800) because the SPL grew over 1200 bytes bigger. It might work better, or just be chance, but it boots from SPI 0.3s slower. So I leave this out of this patch. Changed since v2: - added CONFIG_SPL_DM_SEQ_ALIAS to keep spi1 numeration consistent between SPL and U-Boot Changed since v1: - include CONFIG_SF_DEFAULT_BUS=1 now that numeration will be unified between U-Boot and SPL (at patch 5/5) Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Signed-off-by: Xavier Drudis Ferran Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 18 ++++++++++++++++++ configs/rock-pi-4-rk3399_defconfig | 22 ++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi index c17e769f64..4c2fe8f6bc 100644 --- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi @@ -15,3 +15,21 @@ &vdd_log { regulator-init-microvolt = <950000>; }; + +&spi1 { + status = "okay"; + spi-max-frequency = <40000000>; + spi-activate-delay = <12000>; /* 12 ms */ + + norflash: flash@0 { + compatible = "rockchip,spidev", "jedec,spi-nor"; + reg = <0>; + + spi-max-frequency = <40000000>; + spi-cpha; + spi-cpol; + + status = "okay"; + u-boot,dm-pre-reloc; + }; +}; diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index cf2e9fbde3..d5fadcb64f 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -10,6 +10,8 @@ CONFIG_ROCKCHIP_RK3399=y CONFIG_TARGET_EVB_RK3399=y CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -28,6 +30,10 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_SPI_FLASH_MTD=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0xb0000 CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -40,6 +46,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -48,21 +55,36 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_MODE=0x3 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_MTD=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_NVME_PCI=y CONFIG_PCI=y +CONFIG_SPL_PHY=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y From patchwork Wed Jul 20 15:42:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xavier Drudis Ferran X-Patchwork-Id: 1658709 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Lp0Mc5TDMz9sFr for ; Thu, 21 Jul 2022 01:42:52 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0B0E182EEA; Wed, 20 Jul 2022 17:42:46 +0200 (CEST) Authentication-Results: phobos.denx.de; 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Wed, 20 Jul 2022 17:42:40 +0200 (CEST) X-Barracuda-Envelope-From: xdrudis@tinet.cat X-Barracuda-Effective-Source-IP: smtp01.tinet.cat[195.77.216.131] X-Barracuda-Apparent-Source-IP: 195.77.216.131 Received: from begut (99.red-79-152-185.dynamicip.rima-tde.net [79.152.185.99]) by smtp01.tinet.cat (Postfix) with ESMTPSA id 275E9605D0AC; Wed, 20 Jul 2022 17:42:40 +0200 (CEST) Date: Wed, 20 Jul 2022 17:42:38 +0200 From: Xavier Drudis Ferran To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R Subject: [PATCH v3 3/4] spi-nor: Adapt soft reset to XTX25F32B in Rock Pi 4 rev 1.4 Message-ID: <20220720154237.GG2049@begut> X-ASG-Orig-Subj: [PATCH v3 3/4] spi-nor: Adapt soft reset to XTX25F32B in Rock Pi 4 rev 1.4 References: <20220720153610.GD2049@begut> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220720153610.GD2049@begut> User-Agent: Mutt/1.10.1 (2018-07-13) X-Barracuda-Connect: smtp01.tinet.cat[195.77.216.131] X-Barracuda-Start-Time: 1658331760 X-Barracuda-URL: https://webmail.tinet.cat:443/cgi-mod/mark.cgi X-Barracuda-Scan-Msg-Size: 8037 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: SPAM GLOBAL 1.0000 1.0000 4.3430 X-Barracuda-Spam-Score: 4.84 X-Barracuda-Spam-Status: No, SCORE=4.84 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=6.0 KILL_LEVEL=8.0 tests=BSF_RULE7568M X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.99510 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- 0.50 BSF_RULE7568M Custom Rule 7568M X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean XTX25F32B does not use octal mode and accepts soft reset, despite its SFDP tables. Soft reset at U-Boot exit seems to be required to write to /dev/mtd0 from flashrom in linux. Soft reset at U-Boot start seems to help booting from SPI (at least with the dts properties I'm using). The first soft reset is done before the flash id is read and the fixups can be called, and v1 of this patch would now fail in Rock Pi 4 because of unsupported operation if tried with SNOR_PROTO_8_8_8_DTR. This was since commit 5752d6ae8daa ("spi: spi-mem: add spi_mem_dtr_supports_op()") by Pratyush Yadav. So try a few modes until SNOR_PROTO_1_1_1 works and then remember the reset_proto. This tries to be useful for other boards, but I still don't know any other that needs it and what would work there. Changed since v2: - none (rebase) Changed since v1: - Generalization. First soft reset with SNOR_PROTO_8_8_8_DTR stopped working since the improvement by Pratyush Yadav. Instead of trying 8_8_8_DTR always at first reset, and force 1_1_1 once XTX25F32B is detected (so, for last reset) do a generic loop for any chip trying protocols until one is supported and starting by the 8_8_8_DTR protocol (the one previously used). This leverages the fixed supports_op() to take into account controller and device. fixups can be called, and it would now fail in Rock Pi 4 because of unsupported operation if tried with SNOR_PROTO_8_8_8_DTR. So try a few modes until SNOR_PROTO_1_1_1 works and then remember the reset_proto. This tries to be useful for other boards, but I still don't know any other that needs it and what would work there. Signed-off-by: Xavier Drudis Ferran Cc: Jagan Teki Cc: Vignesh R --- drivers/mtd/spi/spi-nor-core.c | 98 ++++++++++++++++++++++++++++++---- include/linux/mtd/spi-nor.h | 5 ++ 2 files changed, 92 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 8a226a7af5..17f0cb51fb 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3575,6 +3575,18 @@ static struct spi_nor_fixups mt35xu512aba_fixups = { }; #endif /* CONFIG_SPI_FLASH_MT35XU */ +#ifdef CONFIG_SPI_FLASH_XTX +static void xtx25f32b_post_sfdp_fixup(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) +{ + nor->flags |= SNOR_F_SOFT_RESET; +} + +static struct spi_nor_fixups xtx25f32b_fixups = { + .post_sfdp = xtx25f32b_post_sfdp_fixup, +}; +#endif + #if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX) /** * spi_nor_macronix_octal_dtr_enable() - Enable octal DTR on Macronix flashes. @@ -3733,6 +3745,53 @@ static int spi_nor_init(struct spi_nor *nor) } #ifdef CONFIG_SPI_FLASH_SOFT_RESET +/** + * spi_nor_soft_reset_setup_op() - Initial setup of op for soft + * reset. Initializes nor->reset_proto iff needed. + * + * @nor: the spi_nor structure nor->reset_proto will be used or if + * null, it'll be assigned the used protocol, from a few + * protocols that get tried for device and controller + * support. + * + * @opcode operation code for soft reset (or soft reset enable, + * we currently assume they work the same in all systems) + * + * @op: pointer to operation struct to set up for reset or reset + * enable. + */ +static void spi_nor_soft_reset_setup_op(struct spi_nor *nor, u16 opcode, struct spi_mem_op *op) +{ + enum spi_nor_protocol reset_proto; + /** + * admitedly arbitrary list, to be improved if there's + * new knowledge of what works in different systems + */ + enum spi_nor_protocol reset_proto_candidates[] = { + SNOR_PROTO_8_8_8_DTR, SNOR_PROTO_1_1_1_DTR, SNOR_PROTO_8_8_8, + SNOR_PROTO_4_4_4, SNOR_PROTO_2_2_2, SNOR_PROTO_1_1_1 + }; + + if (nor->reset_proto) { + *op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DATA); + spi_nor_setup_op(nor, op, nor->reset_proto); + } else { + for (int i = 0; i < ARRAY_SIZE(reset_proto_candidates) && !nor->reset_proto ; i++) { + reset_proto = reset_proto_candidates[i]; + *op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DATA); + spi_nor_setup_op(nor, op, reset_proto); + if (spi_mem_supports_op(nor->spi, op)) + nor->reset_proto = reset_proto; + } + } +} + /** * spi_nor_soft_reset() - perform the JEDEC Software Reset sequence * @nor: the spi_nor structure @@ -3756,11 +3815,7 @@ static int spi_nor_soft_reset(struct spi_nor *nor) #endif /* SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT */ } - op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_NO_ADDR, - SPI_MEM_OP_NO_DATA); - spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + spi_nor_soft_reset_setup_op(nor, SPINOR_OP_SRSTEN, &op); ret = spi_mem_exec_op(nor->spi, &op); if (ret) { dev_warn(nor->dev, "Software reset enable failed: %d\n", ret); @@ -3771,7 +3826,7 @@ static int spi_nor_soft_reset(struct spi_nor *nor) SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_NO_ADDR, SPI_MEM_OP_NO_DATA); - spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + spi_nor_setup_op(nor, &op, nor->reset_proto); ret = spi_mem_exec_op(nor->spi, &op); if (ret) { dev_warn(nor->dev, "Software reset failed: %d\n", ret); @@ -3789,18 +3844,34 @@ out: nor->cmd_ext_type = ext; return ret; } -#endif /* CONFIG_SPI_FLASH_SOFT_RESET */ + +static bool flash_supports_proto(const struct flash_info *flash, enum spi_nor_protocol proto) +{ + switch (spi_nor_get_protocol_data_nbits(proto)) { + case 8: + return flash->flags & (spi_nor_protocol_is_dtr(proto) + ? SPI_NOR_OCTAL_DTR_READ + : SPI_NOR_OCTAL_READ); + case 4: return flash->flags & SPI_NOR_QUAD_READ; + case 2: return flash->flags & SPI_NOR_DUAL_READ; + default: + return 1; + } +} int spi_nor_remove(struct spi_nor *nor) { -#ifdef CONFIG_SPI_FLASH_SOFT_RESET - if (nor->info->flags & SPI_NOR_OCTAL_DTR_READ && + if (flash_supports_proto(nor->info, nor->reset_proto) && nor->flags & SNOR_F_SOFT_RESET) return spi_nor_soft_reset(nor); -#endif - return 0; } +#else /* !CONFIG_SPI_FLASH_SOFT_RESET */ +int spi_nor_remove(struct spi_nor *nor) +{ + return 0; +} +#endif /* CONFIG_SPI_FLASH_SOFT_RESET */ void spi_nor_set_fixups(struct spi_nor *nor) { @@ -3835,6 +3906,11 @@ void spi_nor_set_fixups(struct spi_nor *nor) #if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX) nor->fixups = ¯onix_octal_fixups; #endif /* SPI_FLASH_MACRONIX */ + +#ifdef CONFIG_SPI_FLASH_XTX + if (!strcmp(nor->info->name, "xt25f32b")) + nor->fixups = &xtx25f32b_fixups; +#endif } int spi_nor_scan(struct spi_nor *nor) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 2595bad9df..4fc81e7b8d 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -501,6 +501,8 @@ struct spi_flash { * @read_proto: the SPI protocol for read operations * @write_proto: the SPI protocol for write operations * @reg_proto the SPI protocol for read_reg/write_reg/erase operations + * @reset_proto: The SPI protocol for soft reset to return to state expected + * by OS before running the OS (at remove time) or at sf probe * @cmd_buf: used by the write_reg * @cmd_ext_type: the command opcode extension for DTR mode. * @fixups: flash-specific fixup hooks. @@ -546,6 +548,9 @@ struct spi_nor { enum spi_nor_protocol read_proto; enum spi_nor_protocol write_proto; enum spi_nor_protocol reg_proto; +#ifdef CONFIG_SPI_FLASH_SOFT_RESET + enum spi_nor_protocol reset_proto; +#endif bool sst_write_second; u32 flags; u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; From patchwork Wed Jul 20 15:43:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xavier Drudis Ferran X-Patchwork-Id: 1658710 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Lp0Nd16Mhz9sFr for ; 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dmarc=none (p=none dis=none) header.from=tinet.cat Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=xdrudis@tinet.cat X-ASG-Debug-ID: 1658331816-12aaf258c3a7a370001-4l7tJC Received: from smtp01.tinet.cat (smtp01.tinet.cat [195.77.216.131]) by mx1.tinet.cat with ESMTP id uuyi1uDN4owLNKDM; Wed, 20 Jul 2022 17:43:36 +0200 (CEST) X-Barracuda-Envelope-From: xdrudis@tinet.cat X-Barracuda-Effective-Source-IP: smtp01.tinet.cat[195.77.216.131] X-Barracuda-Apparent-Source-IP: 195.77.216.131 Received: from begut (99.red-79-152-185.dynamicip.rima-tde.net [79.152.185.99]) by smtp01.tinet.cat (Postfix) with ESMTPSA id 6DC5B605D0AC; Wed, 20 Jul 2022 17:43:36 +0200 (CEST) Date: Wed, 20 Jul 2022 17:43:35 +0200 From: Xavier Drudis Ferran To: u-boot@lists.denx.de Cc: Jagan Teki Subject: [PATCH v3 4/4] spi: spi-mem: Allow address 0 for SPI mem operations Message-ID: <20220720154335.GH2049@begut> X-ASG-Orig-Subj: [PATCH v3 4/4] spi: spi-mem: Allow address 0 for SPI mem operations References: <20220720153610.GD2049@begut> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220720153610.GD2049@begut> User-Agent: Mutt/1.10.1 (2018-07-13) X-Barracuda-Connect: smtp01.tinet.cat[195.77.216.131] X-Barracuda-Start-Time: 1658331816 X-Barracuda-URL: https://webmail.tinet.cat:443/cgi-mod/mark.cgi X-Barracuda-Scan-Msg-Size: 3711 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.5052 1.0000 0.7500 X-Barracuda-Spam-Score: 0.75 X-Barracuda-Spam-Status: No, SCORE=0.75 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=6.0 KILL_LEVEL=8.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.99510 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Trying to boot my Rock Pi 4B from its XTX SPI NOR Flash failed when my custom compiled TF-A had a load address of 0. The same TF-A booted correctly from MMC. Add a local variable to spi_mem_exec_op() to determine operation direction, instead of testing rx_buf or tx_buf for null value, so that a buffer at RAM address 0 is accepted. This commit also cuts short a debug dump of the image loaded to show only the first 0x1000 and the last 0x100 bytes, and not swamping the serial log. When adding the #define DEBUG to the .c file one can change these limits at the same time if they don't fit. Changed since v2: - no changes Changed since v1: - no changes Signed-off-by: Xavier Drudis Ferran Cc: Jagan Teki --- drivers/spi/spi-mem.c | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 9c1ede1b61..4dc90addb3 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -21,6 +21,8 @@ #include #include #include +#define DEBUG_DUMP_START_LENGTH 0x1000 +#define DEBUG_DUMP_END_LENGTH 0x100 #endif #ifndef __UBOOT__ @@ -373,12 +375,21 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) if (msg.actual_length != totalxferlen) return -EIO; #else + enum spi_mem_data_dir dir = SPI_MEM_NO_DATA; if (op->data.nbytes) { - if (op->data.dir == SPI_MEM_DATA_IN) + dir = op->data.dir; + if (dir == SPI_MEM_DATA_IN) { rx_buf = op->data.buf.in; - else + } else { tx_buf = op->data.buf.out; + /** + * keep old behaviour, to assume SPI_MEM_DATA_OUT + * if ever data.nbytes!=0 but data.dir==SPI_MEM_NO_DATA + * (hopefully never) + */ + dir = SPI_MEM_DATA_OUT; + } } op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; @@ -410,7 +421,7 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) /* 1st transfer: opcode + address + dummy cycles */ flag = SPI_XFER_BEGIN; /* Make sure to set END bit if no tx or rx data messages follow */ - if (!tx_buf && !rx_buf) + if (dir == SPI_MEM_NO_DATA) flag |= SPI_XFER_END; ret = spi_xfer(slave, op_len * 8, op_buf, NULL, flag); @@ -418,7 +429,7 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) return ret; /* 2nd transfer: rx or tx data path */ - if (tx_buf || rx_buf) { + if (dir != SPI_MEM_NO_DATA) { ret = spi_xfer(slave, op->data.nbytes * 8, tx_buf, rx_buf, SPI_XFER_END); if (ret) @@ -430,10 +441,17 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) for (i = 0; i < pos; i++) debug("%02x ", op_buf[i]); debug("| [%dB %s] ", - tx_buf || rx_buf ? op->data.nbytes : 0, - tx_buf || rx_buf ? (tx_buf ? "out" : "in") : "-"); - for (i = 0; i < op->data.nbytes; i++) - debug("%02x ", tx_buf ? tx_buf[i] : rx_buf[i]); + op->data.nbytes, + dir == SPI_MEM_DATA_IN ? "in" : (dir == SPI_MEM_DATA_OUT ? "out" : "-")); + for (i = 0; i < op->data.nbytes && i < DEBUG_DUMP_START_LENGTH ; i++) + debug("%02x ", dir == SPI_MEM_DATA_OUT ? tx_buf[i] : rx_buf[i]); + if (op->data.nbytes > DEBUG_DUMP_END_LENGTH && op->data.nbytes > DEBUG_DUMP_START_LENGTH && + i < op->data.nbytes - DEBUG_DUMP_END_LENGTH) { + debug(" ... "); + i = op->data.nbytes - DEBUG_DUMP_END_LENGTH; + } + for (; i < op->data.nbytes ; i++) + debug("%02x ", dir == SPI_MEM_DATA_OUT ? tx_buf[i] : rx_buf[i]); debug("[ret %d]\n", ret); if (ret < 0)