From patchwork Wed Feb 28 13:24:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien DESSENNE X-Patchwork-Id: 879140 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zrxBf22ppz9s2g for ; Thu, 1 Mar 2018 00:25:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752469AbeB1NZM (ORCPT ); Wed, 28 Feb 2018 08:25:12 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:51914 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752460AbeB1NZL (ORCPT ); Wed, 28 Feb 2018 08:25:11 -0500 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w1SDNkw6030661; Wed, 28 Feb 2018 14:24:50 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2gax28mmft-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 28 Feb 2018 14:24:50 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4114931; Wed, 28 Feb 2018 13:24:50 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1DDCB2BA0; Wed, 28 Feb 2018 13:24:50 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Wed, 28 Feb 2018 14:24:50 +0100 Received: from localhost (10.201.23.25) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Wed, 28 Feb 2018 14:24:49 +0100 From: Fabien Dessenne To: Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue , Jassi Brar , "Ludovic Barre" , , , CC: Benjamin Gaignard , Loic Pallardy , Arnaud Pouliquen Subject: [PATCH 1/2] dt-bindings: mailbox: add STMicroelectronics STM32 IPCC binding Date: Wed, 28 Feb 2018 14:24:29 +0100 Message-ID: <1519824270-7134-2-git-send-email-fabien.dessenne@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519824270-7134-1-git-send-email-fabien.dessenne@st.com> References: <1519824270-7134-1-git-send-email-fabien.dessenne@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.25] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-28_07:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a binding for the STMicroelectronics STM32 IPCC block exposing a mailbox mechanism between two processors. Signed-off-by: Fabien Dessenne Signed-off-by: Ludovic Barre --- .../devicetree/bindings/mailbox/stm32-ipcc.txt | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt diff --git a/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt b/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt new file mode 100644 index 0000000..2321689 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt @@ -0,0 +1,48 @@ +* STMicroelectronics STM32 IPCC (Inter-Processor Communication Controller) + +The IPCC block provides a non blocking signaling mechanism to post and +retrieve messages in an atomic way between two processors. +It provides the signaling for N bidirectionnal channels. The number of channels +(N) can be read from a dedicated register. + +Required properties: +- compatible: Must be "st,stm32-ipcc" +- reg: Register address range (base address and length) +- st,proc_id: Processor id using the mailbox (0 or 1) +- clocks: Input clock +- interrupt-names: List of names for the interrupts described by the interrupt + property. Must contain the following entries: + - "rx" + - "tx" +- interrupts: Interrupt specifiers for "rx channel occupied" and "tx channel + free" +- #mbox-cells: Number of cells required for the mailbox specifier. Must be 1. + The data contained in the mbox specifier of the "mboxes" + property in the client node is the mailbox channel index. + +Optional properties: +- wakeup-source: Flag to indicate whether this device can wake up the system +- interrupts: Wakeup interrupt used to wake up the system. +- interrupt-names: "wakeup" for the wakeup interrupt. + + + +Example: + ipcc: mailbox@4c001000 { + compatible = "st,stm32-ipcc"; + #mbox-cells = <1>; + reg = <0x4c001000 0x400>; + st,proc_id = <0>; + interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>, + <&intc GIC_SPI 101 IRQ_TYPE_NONE>, + <&aiec 62 1>; + interrupt-names = "rx", "tx", "wakeup"; + clocks = <&rcc_clk IPCC>; + wakeup-source; + } + +Client: + mbox_test { + ... + mboxes = <&ipcc 0>, <&ipcc 1>; + };