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Miller" , Jakub Kicinski , Madalin Bucur , netdev@vger.kernel.org Cc: Paolo Abeni , Eric Dumazet , linux-arm-kernel@lists.infradead.org, Russell King , linux-kernel@vger.kernel.org, Sean Anderson , Kishon Vijay Abraham I , Krzysztof Kozlowski , Rob Herring , Vinod Koul , devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH net-next v3 01/47] dt-bindings: phy: Add Lynx 10G phy binding Date: Fri, 15 Jul 2022 17:59:08 -0400 Message-Id: <20220715215954.1449214-2-sean.anderson@seco.com> X-Mailer: git-send-email 2.35.1.1320.gc452695387.dirty In-Reply-To: <20220715215954.1449214-1-sean.anderson@seco.com> References: <20220715215954.1449214-1-sean.anderson@seco.com> X-ClientProxiedBy: CH2PR10CA0009.namprd10.prod.outlook.com (2603:10b6:610:4c::19) To VI1PR03MB4973.eurprd03.prod.outlook.com (2603:10a6:803:c5::12) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6240f76b-e7a4-4004-5bbd-08da66ad6466 X-MS-TrafficTypeDiagnostic: DU0PR03MB8598:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ATpelNNnp6VEa6TR42bVtnGYs/9iMOcFopwmShzjY5jI+hEdUuB0ArHGzRgv0Ypjzabr56SlY4jm5JjMtkSNfgDdgN4coUHiY+Th3qmY/CNrVfnd7Ghpe+CSAAGvYzUfYkaFRPvzyH28igtk44CK8M3IHzmt4fshkPYviRVk8QgLza5b5fTCRNuUltyGcHdQ/BgU1H5FSiW9FyMDSpKfSvfU1IEqpLLEPYDu2kmJ9C9M9VJ1lvauGSWKMJULW9QCth20komEPiyeq7TUf8SoppAFJpEFCvr4hg6mvDbakiig4vp6/JwuAz6/PrW8kRxL0oiDCOGmfhMaGFyyAG4CLjaGKIy2PzAjl66yVHrMGBRGPutNJnFjfnzWFopUngk/MzrMhqKGPePYpkPTQrUIwiVVHHPu+NrOKZzr4OsHjQ8/ZB/aBf23fQn2D/eKbfr3fsO0JiBp8xa9skI84hhtn+JfnIGWfzqn1GiwS60bDrD5DsjInuhklPypb4Gs1sjyBDiCqTSTz0rW3ki2xkBnaR938eeYyKlEKTyy9Q8tZcOVYHhWfHG71HAW1bWCHYx9voiHGayyJ50pYKdgEiQQ8AVXZEH7FSv8kGvTe50YPbTFIdACYs51GJ7fE6Z23WmhIMxSyQL2jJYay4Qzbau3xNf1Tabyz9S9VTTQkBMFF4zvqFNBi/0ee08+wHdmL4KvdLxufkPbnDJi0NhyZ3szfa1ixCm/narJIqwZ2Zn0taBT3s4gG6nPOEgFM75zRQfwqQq0nKPl3Un82rHeEfg7JGrvC+bVzy6tGVAyQIUh6O6ho4unNOJ/Mulnea7dSI7B+Zse2psKA1VlnoIRDc89foCvNs678ofDVyvT5FPZZkUpPkoSfzSI5YIpLRJPpcvrsqocJLo2HdJBrA/Z9q8F047SinZQIuHYW1fJzNkfhyJIs1jePBHb59vSV/RnRgheGXy7M7zPiV2y6zX7+lOOwRMOSxpaa/6qORedvtBZ9lrbWK7KgAoHZaAlZZHtd6hhL0CgzIk78DjK4JOfZIYpkQdD6Imu87qCQDVMH/W6ujV3R1BEJfMvICdiuLx5Ze0aPvaZQ921a+Yt/RnB8AzZb1MYFArD+Xu/NslYAN8ZWRjon7hBQNGEiQtE0waQ0qa5NcQSwKYtU2jH5R/5yG4QJzPqZhaHWXk8gnX9qGUkbG2GG5TVmTKeMTHUy5jy//beSUDhnofW3Hay5Qg1kzr+IXh6twJqfraBiD6axRQaQ7ZVbIYeXlwlbmea4fcr/+KBDNOrGncx1O/CdvmrCZmrQFX4SXjiwU5h2OMD/UW3T5BLSlzZXgnt9vhYZg19FsImG3jP6UyrexBchxO4ASWaIWdJfDeQSl+1FugfCLfGExY6DaPzRZ74gJsLL3051jEBtEB1J/Yw8JIlhsYNEkYer3CJ5CU3mXAtHrexJoCsZ18CdwSz6MrHobAbLE4OKJiSE1awBYSjwNXRFirq8tzE0gZgYKk2urPz9UP8AV+nVKgq6ucQ+Hc8vZ0cH6eePqvkHst+JCtiDuytaOh7XfVWi+Vfkwue5IAV/j9WYrPk6jtZUl7POGMYYPAVYmhgGLuSZ1FemV5+885TDF5S/iwg9A== X-OriginatorOrg: seco.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6240f76b-e7a4-4004-5bbd-08da66ad6466 X-MS-Exchange-CrossTenant-AuthSource: VI1PR03MB4973.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2022 22:00:12.9588 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: bebe97c3-6438-442e-ade3-ff17aa50e733 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Me/zVX2WDrRCdj8zMuw17NDmsft3zh9cXL63w3zHVtqavuPFLbWpbiHLzhYSRA84fj93nzT+n3uiLnt/Yo27iQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR03MB8598 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a binding for the SerDes module found on QorIQ processors. The phy reference has two cells, one for the first lane and one for the last. This should allow for good support of multi-lane protocols when (if) they are added. There is no protocol option, because the driver is designed to be able to completely reconfigure lanes at runtime. Generally, the phy consumer can select the appropriate protocol using set_mode. For the most part there is only one protocol controller (consumer) per lane/protocol combination. The exception to this is the B4860 processor, which has some lanes which can be connected to multiple MACs. For that processor, I anticipate the easiest way to resolve this will be to add an additional cell with a "protocol controller instance" property. Each serdes has a unique set of supported protocols (and lanes). The support matrix is configured in the device tree. The format of each PCCR (protocol configuration register) is modeled. Although the general format is typically the same across different SoCs, the specific supported protocols (and the values necessary to select them) are particular to individual SerDes. A nested structure is used to reduce duplication of data. There are two PLLs, each of which can be used as the master clock for each lane. Each PLL has its own reference. For the moment they are required, because it simplifies the driver implementation. Absent reference clocks can be modeled by a fixed-clock with a rate of 0. Signed-off-by: Sean Anderson --- Changes in v3: - Manually expand yaml references - Add mode configuration to device tree Changes in v2: - Rename to fsl,lynx-10g.yaml - Refer to the device in the documentation, rather than the binding - Move compatible first - Document phy cells in the description - Allow a value of 1 for phy-cells. This allows for compatibility with the similar (but according to Ioana Ciornei different enough) lynx-28g binding. - Remove minItems - Use list for clock-names - Fix example binding having too many cells in regs - Add #clock-cells. This will allow using assigned-clocks* to configure the PLLs. - Document the structure of the compatible strings .../devicetree/bindings/phy/fsl,lynx-10g.yaml | 311 ++++++++++++++++++ 1 file changed, 311 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml new file mode 100644 index 000000000000..a2c37225bb67 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml @@ -0,0 +1,311 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Lynx 10G SerDes + +maintainers: + - Sean Anderson + +description: | + These Lynx "SerDes" devices are found in NXP's QorIQ line of processors. The + SerDes provides up to eight lanes. Each lane may be configured individually, + or may be combined with adjacent lanes for a multi-lane protocol. The SerDes + supports a variety of protocols, including up to 10G Ethernet, PCIe, SATA, and + others. The specific protocols supported for each lane depend on the + particular SoC. + +definitions: + fsl,cfg: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + description: | + The configuration value to program into the field. + + fsl,first-lane: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + description: | + The first lane in the group configured by fsl,cfg. This lane will have + the FIRST_LANE bit set in GCR0. The reset direction will also be set + based on whether this property is less than or greater than + fsl,last-lane. + + fsl,last-lane: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + description: | + The last lane configured by fsl,cfg. If this property is absent, + then it will default to the value of fsl,first-lane. + +properties: + compatible: + items: + - enum: + - fsl,ls1046a-serdes + - fsl,ls1088a-serdes + - const: fsl,lynx-10g + + "#clock-cells": + const: 1 + description: | + The cell contains the index of the PLL, starting from 0. Note that when + assigning a rate to a PLL, the PLLs' rates are divided by 1000 to avoid + overflow. A rate of 5000000 corresponds to 5GHz. + + "#phy-cells": + minimum: 1 + maximum: 2 + description: | + The cells contain the following arguments: + - The first lane in the group. Lanes are numbered based on the register + offsets, not the I/O ports. This corresponds to the letter-based ("Lane + A") naming scheme, and not the number-based ("Lane 0") naming scheme. On + most SoCs, "Lane A" is "Lane 0", but not always. + - Last lane. For single-lane protocols, this should be the same as the + first lane. + If no lanes in a SerDes can be grouped, then #phy-cells may be 1, and the + first cell will specify the only lane in the group. + + clocks: + maxItems: 2 + description: | + Clock for each PLL reference clock input. + + clock-names: + minItems: 2 + maxItems: 2 + items: + enum: + - ref0 + - ref1 + + reg: + maxItems: 1 + +patternProperties: + '^pccr-': + type: object + + description: | + One of the protocol configuration registers (PCCRs). These contains + several fields, each of which mux a particular protocol onto a particular + lane. + + properties: + fsl,pccr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The index of the PCCR. This is the same as the register name suffix. + For example, a node for PCCRB would use a value of '0xb' for an + offset of 0x22C (0x200 + 4 * 0xb). + + patternProperties: + '^(q?sgmii|xfi|pcie|sata)-': + type: object + + description: | + A configuration field within a PCCR. Each field configures one + protocol controller. The value of the field determines the lanes the + controller is connected to, if any. + + properties: + fsl,index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The index of the field. This corresponds to the suffix in the + documentation. For example, PEXa would be 0, PEXb 1, etc. + Generally, higher fields occupy lower bits. + + If there are any subnodes present, they will be preferred over + fsl,cfg et. al. + + fsl,cfg: + $ref: "#/definitions/fsl,cfg" + + fsl,first-lane: + $ref: "#/definitions/fsl,first-lane" + + fsl,last-lane: + $ref: "#/definitions/fsl,last-lane" + + fsl,proto: + $ref: /schemas/types.yaml#/definitions/string + enum: + - sgmii + - sgmii25 + - qsgmii + - xfi + - pcie + - sata + description: | + Indicates the basic group protocols supported by this field. + Individual protocols are selected by configuring the protocol + controller. + + - sgmii: 1000BASE-X, SGMII, and 1000BASE-KX (depending on the + SoC) + - sgmii25: 2500BASE-X, 1000BASE-X, SGMII, and 1000BASE-KX + (depending on the SoC) + - qsgmii: QSGMII + - xfi: 10GBASE-R and 10GBASE-KR (depending on the SoC) + - pcie: PCIe + - sata: SATA + + patternProperties: + '^cfg-': + type: object + + description: | + A single field may have multiple values which, when programmed, + connect the protocol controller to different lanes. If this is the + case, multiple sub-nodes may be provided, each describing a + single muxing. + + properties: + fsl,cfg: + $ref: "#/definitions/fsl,cfg" + + fsl,first-lane: + $ref: "#/definitions/fsl,first-lane" + + fsl,last-lane: + $ref: "#/definitions/fsl,last-lane" + + required: + - fsl,cfg + - fsl,first-lane + + dependencies: + fsl,last-lane: + - fsl,first-lane + + additionalProperties: false + + required: + - fsl,index + - fsl,proto + + dependencies: + fsl,last-lane: + - fsl,first-lane + fsl,cfg: + - fsl,first-lane + fsl,first-lane: + - fsl,cfg + + # I would like to require either a config subnode or the config + # properties (and not both), but from what I can tell that can't be + # expressed in json schema. In particular, it is not possible to + # require a pattern property. + + additionalProperties: false + + required: + - fsl,pccr + + additionalProperties: false + +required: + - "#clock-cells" + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + - | + serdes1: phy@1ea0000 { + #clock-cells = <1>; + #phy-cells = <2>; + compatible = "fsl,ls1088a-serdes", "fsl,lynx-10g"; + reg = <0x1ea0000 0x2000>; + clocks = <&clk_100mhz>, <&clk_156_mhz>; + clock-names = "ref0", "ref1"; + assigned-clocks = <&serdes1 0>; + assigned-clock-rates = <5000000>; + + pccr-8 { + fsl,pccr = <0x8>; + + sgmii-0 { + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,first-lane = <3>; + fsl,proto = "sgmii"; + }; + + sgmii-1 { + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,first-lane = <2>; + fsl,proto = "sgmii"; + }; + + sgmii-2 { + fsl,index = <2>; + fsl,cfg = <0x1>; + fsl,first-lane = <1>; + fsl,proto = "sgmii25"; + }; + + sgmii-3 { + fsl,index = <3>; + fsl,cfg = <0x1>; + fsl,first-lane = <0>; + fsl,proto = "sgmii25"; + }; + }; + + pccr-9 { + fsl,pccr = <0x9>; + + qsgmii-0 { + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,first-lane = <3>; + fsl,proto = "qsgmii"; + }; + + qsgmii-1 { + fsl,index = <1>; + fsl,proto = "qsgmii"; + + cfg-1 { + fsl,cfg = <0x1>; + fsl,first-lane = <2>; + }; + + cfg-2 { + fsl,cfg = <0x2>; + fsl,first-lane = <0>; + }; + }; + }; + + pccr-b { + fsl,pccr = <0xb>; + + xfi-0 { + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,first-lane = <1>; + fsl,proto = "xfi"; + }; + + xfi-1 { + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,first-lane = <0>; + fsl,proto = "xfi"; + }; + }; + }; +... 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Signed-off-by: Sean Anderson Reviewed-by: Rob Herring --- Changes in v3: - Incorperate some minor changes into the first FMan binding commit Changes in v2: - New .../bindings/net/fsl,fman-dtsec.yaml | 145 ++++++++++++++++++ .../devicetree/bindings/net/fsl-fman.txt | 128 +--------------- 2 files changed, 146 insertions(+), 127 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml diff --git a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml new file mode 100644 index 000000000000..78579ef839bf --- /dev/null +++ b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP FMan MAC + +maintainers: + - Madalin Bucur + +description: | + Each FMan has several MACs, each implementing an Ethernet interface. Earlier + versions of FMan used the Datapath Three Speed Ethernet Controller (dTSEC) for + 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller + (10GEC) for 10 Gbit/s speeds. Later versions of FMan use the Multirate + Ethernet Media Access Controller (mEMAC) to handle all speeds. + +properties: + compatible: + enum: + - fsl,fman-dtsec + - fsl,fman-xgec + - fsl,fman-memac + + cell-index: + maximum: 64 + description: | + FManV2: + register[bit] MAC cell-index + ============================================================ + FM_EPI[16] XGEC 8 + FM_EPI[16+n] dTSECn n-1 + FM_NPI[11+n] dTSECn n-1 + n = 1,..,5 + + FManV3: + register[bit] MAC cell-index + ============================================================ + FM_EPI[16+n] mEMACn n-1 + FM_EPI[25] mEMAC10 9 + + FM_NPI[11+n] mEMACn n-1 + FM_NPI[10] mEMAC10 9 + FM_NPI[11] mEMAC9 8 + n = 1,..8 + + FM_EPI and FM_NPI are located in the FMan memory map. + + 2. SoC registers: + + - P2041, P3041, P4080 P5020, P5040: + register[bit] FMan MAC cell + Unit index + ============================================================ + DCFG_DEVDISR2[7] 1 XGEC 8 + DCFG_DEVDISR2[7+n] 1 dTSECn n-1 + DCFG_DEVDISR2[15] 2 XGEC 8 + DCFG_DEVDISR2[15+n] 2 dTSECn n-1 + n = 1,..5 + + - T1040, T2080, T4240, B4860: + register[bit] FMan MAC cell + Unit index + ============================================================ + DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1 + DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1 + n = 1,..6,9,10 + + EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in + the specific SoC "Device Configuration/Pin Control" Memory + Map. + + reg: + maxItems: 1 + + fsl,fman-ports: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 2 + description: | + An array of two references: the first is the FMan RX port and the second + is the TX port used by this MAC. + + ptp-timer: + $ref: /schemas/types.yaml#/definitions/phandle + description: A reference to the IEEE1588 timer + + pcsphy-handle: + $ref: /schemas/types.yaml#/definitions/phandle + description: A reference to the PCS (typically found on the SerDes) + + tbi-handle: + $ref: /schemas/types.yaml#/definitions/phandle + description: A reference to the (TBI-based) PCS + +required: + - compatible + - cell-index + - reg + - fsl,fman-ports + - ptp-timer + +allOf: + - $ref: ethernet-controller.yaml# + - if: + properties: + compatible: + contains: + const: fsl,fman-dtsec + then: + required: + - tbi-handle + - if: + properties: + compatible: + contains: + const: fsl,fman-memac + then: + required: + - pcsphy-handle + +additionalProperties: false + +examples: + - | + ethernet@e0000 { + compatible = "fsl,fman-dtsec"; + cell-index = <0>; + reg = <0xe0000 0x1000>; + fsl,fman-ports = <&fman1_rx8 &fman1_tx28>; + ptp-timer = <&ptp_timer>; + tbi-handle = <&tbi0>; + }; + - | + ethernet@e8000 { + cell-index = <4>; + compatible = "fsl,fman-memac"; + reg = <0xe8000 0x1000>; + fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>; + ptp-timer = <&ptp_timer0>; + pcsphy-handle = <&pcsphy4>; + phy-handle = <&sgmii_phy1>; + phy-connection-type = "sgmii"; + }; +... diff --git a/Documentation/devicetree/bindings/net/fsl-fman.txt b/Documentation/devicetree/bindings/net/fsl-fman.txt index 801efc7d6818..b9055335db3b 100644 --- a/Documentation/devicetree/bindings/net/fsl-fman.txt +++ b/Documentation/devicetree/bindings/net/fsl-fman.txt @@ -232,133 +232,7 @@ port@81000 { ============================================================================= FMan dTSEC/XGEC/mEMAC Node -DESCRIPTION - -mEMAC/dTSEC/XGEC are the Ethernet network interfaces - -PROPERTIES - -- compatible - Usage: required - Value type: - Definition: A standard property. - Must include one of the following: - - "fsl,fman-dtsec" for dTSEC MAC - - "fsl,fman-xgec" for XGEC MAC - - "fsl,fman-memac" for mEMAC MAC - -- cell-index - Usage: required - Value type: - Definition: Specifies the MAC id. - - The cell-index value may be used by the FMan or the SoC, to - identify the MAC unit in the FMan (or SoC) memory map. - In the tables below there's a description of the cell-index - use, there are two tables, one describes the use of cell-index - by the FMan, the second describes the use by the SoC: - - 1. FMan Registers - - FManV2: - register[bit] MAC cell-index - ============================================================ - FM_EPI[16] XGEC 8 - FM_EPI[16+n] dTSECn n-1 - FM_NPI[11+n] dTSECn n-1 - n = 1,..,5 - - FManV3: - register[bit] MAC cell-index - ============================================================ - FM_EPI[16+n] mEMACn n-1 - FM_EPI[25] mEMAC10 9 - - FM_NPI[11+n] mEMACn n-1 - FM_NPI[10] mEMAC10 9 - FM_NPI[11] mEMAC9 8 - n = 1,..8 - - FM_EPI and FM_NPI are located in the FMan memory map. - - 2. SoC registers: - - - P2041, P3041, P4080 P5020, P5040: - register[bit] FMan MAC cell - Unit index - ============================================================ - DCFG_DEVDISR2[7] 1 XGEC 8 - DCFG_DEVDISR2[7+n] 1 dTSECn n-1 - DCFG_DEVDISR2[15] 2 XGEC 8 - DCFG_DEVDISR2[15+n] 2 dTSECn n-1 - n = 1,..5 - - - T1040, T2080, T4240, B4860: - register[bit] FMan MAC cell - Unit index - ============================================================ - DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1 - DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1 - n = 1,..6,9,10 - - EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in - the specific SoC "Device Configuration/Pin Control" Memory - Map. - -- reg - Usage: required - Value type: - Definition: A standard property. - -- fsl,fman-ports - Usage: required - Value type: - Definition: An array of two phandles - the first references is - the FMan RX port and the second is the TX port used by this - MAC. - -- ptp-timer - Usage required - Value type: - Definition: A phandle for 1EEE1588 timer. - -- pcsphy-handle - Usage required for "fsl,fman-memac" MACs - Value type: - Definition: A phandle for pcsphy. - -- tbi-handle - Usage required for "fsl,fman-dtsec" MACs - Value type: - Definition: A phandle for tbiphy. - -EXAMPLE - -fman1_tx28: port@a8000 { - cell-index = <0x28>; - compatible = "fsl,fman-v2-port-tx"; - reg = <0xa8000 0x1000>; -}; - -fman1_rx8: port@88000 { - cell-index = <0x8>; - compatible = "fsl,fman-v2-port-rx"; - reg = <0x88000 0x1000>; -}; - -ptp-timer: ptp_timer@fe000 { - compatible = "fsl,fman-ptp-timer"; - reg = <0xfe000 0x1000>; -}; - -ethernet@e0000 { - compatible = "fsl,fman-dtsec"; - cell-index = <0>; - reg = <0xe0000 0x1000>; - fsl,fman-ports = <&fman1_rx8 &fman1_tx28>; - ptp-timer = <&ptp-timer>; - tbi-handle = <&tbi0>; -}; +Refer to Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml ============================================================================ FMan IEEE 1588 Node From patchwork Fri Jul 15 21:59:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1657057 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; 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That is, if the phy interface is RGMII, it assumed that RGMII is supported. For some interfaces, it is assumed that the RCW/bootloader has set up the SerDes properly. This is generally OK, but restricts runtime reconfiguration. The actual link state is never reported. To address these shortcomings, the driver will need additional information. First, it needs to know how to access the PCS/PMAs (in order to configure them and get the link status). The SGMII PCS/PMA is the only currently-described PCS/PMA. Add the XFI and QSGMII PCS/PMAs as well. The XFI (and 10GBASE-KR) PCS/PMA is a c45 "phy" which sits on the same MDIO bus as SGMII PCS/PMA. By default they will have conflicting addresses, but they are also not enabled at the same time by default. Therefore, we can let the XFI PCS/PMA be the default when phy-connection-type is xgmii. This will allow for backwards-compatibility. QSGMII, however, cannot work with the current binding. This is because the QSGMII PCS/PMAs are only present on one MAC's MDIO bus. At the moment this is worked around by having every MAC write to the PCS/PMA addresses (without checking if they are present). This only works if each MAC has the same configuration, and only if we don't need to know the status. Because the QSGMII PCS/PMA will typically be located on a different MDIO bus than the MAC's SGMII PCS/PMA, there is no fallback for the QSGMII PCS/PMA. Signed-off-by: Sean Anderson --- Changes in v3: - Add vendor prefix 'fsl,' to rgmii and mii properties. - Set maxItems for pcs-names - Remove phy-* properties from example because dt-schema complains and I can't be bothered to figure out how to make it work. - Add pcs-handle as a preferred version of pcsphy-handle - Deprecate pcsphy-handle - Remove mii/rmii properties Changes in v2: - Better document how we select which PCS to use in the default case .../bindings/net/fsl,fman-dtsec.yaml | 53 ++++++++++++++----- .../devicetree/bindings/net/fsl-fman.txt | 5 +- 2 files changed, 43 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml index 78579ef839bf..4abf2f93667e 100644 --- a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml +++ b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml @@ -85,9 +85,39 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: A reference to the IEEE1588 timer + phys: + description: A reference to the SerDes lane(s) + maxItems: 1 + + phy-names: + items: + - const: serdes + pcsphy-handle: - $ref: /schemas/types.yaml#/definitions/phandle - description: A reference to the PCS (typically found on the SerDes) + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 3 + deprecated: true + description: See pcs-handle. + + pcs-handle: + minItems: 1 + maxItems: 3 + description: | + A reference to the various PCSs (typically found on the SerDes). If + pcs-names is absent, and phy-connection-type is "xgmii", then the first + reference will be assumed to be for "xfi". Otherwise, if pcs-names is + absent, then the first reference will be assumed to be for "sgmii". + + pcs-names: + minItems: 1 + maxItems: 3 + items: + enum: + - sgmii + - qsgmii + - xfi + description: The type of each PCS in pcsphy-handle. tbi-handle: $ref: /schemas/types.yaml#/definitions/phandle @@ -100,6 +130,10 @@ required: - fsl,fman-ports - ptp-timer +dependencies: + pcs-names: + - pcs-handle + allOf: - $ref: ethernet-controller.yaml# - if: @@ -110,14 +144,6 @@ allOf: then: required: - tbi-handle - - if: - properties: - compatible: - contains: - const: fsl,fman-memac - then: - required: - - pcsphy-handle additionalProperties: false @@ -138,8 +164,9 @@ examples: reg = <0xe8000 0x1000>; fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>; ptp-timer = <&ptp_timer0>; - pcsphy-handle = <&pcsphy4>; - phy-handle = <&sgmii_phy1>; - phy-connection-type = "sgmii"; + pcs-handle = <&pcsphy4>, <&qsgmiib_pcs1>; + pcs-names = "sgmii", "qsgmii"; + phys = <&serdes1 1>; + phy-names = "serdes"; }; ... diff --git a/Documentation/devicetree/bindings/net/fsl-fman.txt b/Documentation/devicetree/bindings/net/fsl-fman.txt index b9055335db3b..bda4b41af074 100644 --- a/Documentation/devicetree/bindings/net/fsl-fman.txt +++ b/Documentation/devicetree/bindings/net/fsl-fman.txt @@ -320,8 +320,9 @@ For internal PHY device on internal mdio bus, a PHY node should be created. See the definition of the PHY node in booting-without-of.txt for an example of how to define a PHY (Internal PHY has no interrupt line). - For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY. -- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY, - PCS PHY addr must be '0'. +- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY. + The PCS PHY address should correspond to the value of the appropriate + MDEV_PORT. EXAMPLE