From patchwork Fri Jul 15 13:27:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 1656883 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=nextmovesoftware.com header.i=@nextmovesoftware.com header.a=rsa-sha256 header.s=default header.b=k8HXMQuj; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Lkscg4ZpYz9ryY for ; Fri, 15 Jul 2022 23:28:18 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C81D93857358 for ; Fri, 15 Jul 2022 13:28:13 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 4F6713857BB2 for ; Fri, 15 Jul 2022 13:28:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4F6713857BB2 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=GMiy9Q6tdvbYxrxqlk5PZkq6xZ5UOinVyxQcKxPHZZI=; b=k8HXMQujCZWzLdZkqvu/lOva9F ctVKiwPaMZgNpeSu8omgTdUe2LdG81xR/YnuVE7aKJhd2rvq2RMz2xlLIMY+CXX1S2TFMPls8hb0m ZKH2pH+sbxJdgxQVuFhgiDHg7159pirh7cb7LFHF+fjYCe3Xp4c2GQx5Iq5/AzR3pam7TjprCkqBX sMKLLOfMCxYzvA+BcDYfbwfoUTJ74fjsfryPs0BkfmI1ULs+EFvo5Hj3EfoJixCYYGdWrP3o6h7lK hA+/BVNSi4FVNMFHkg3oJoVv4jwyiXECBEddOTT0KmJ84BS5PrS4j754Qn37By6D6DoYKHAe9zJmI slkL7/Pw==; Received: from [185.62.158.67] (port=53993 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oCLMN-00037r-Fx; Fri, 15 Jul 2022 09:27:59 -0400 From: "Roger Sayle" To: "'GCC Patches'" Subject: [x86 PATCH] PR target/106273: Add earlyclobber to *andn3_doubleword_bmi Date: Fri, 15 Jul 2022 14:27:56 +0100 Message-ID: <011f01d8984e$b3a27870$1ae76950$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdiYTcIeKswFtFi4RtqZ7EEMySum/w== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, HTML_MESSAGE, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch resolves PR target/106273 which is a wrong code regression caused by the recent reorganization to split doubleword operations after reload on x86. For the failing test case, the constraints on the andnti3_doubleword_bmi pattern allow reload to allocate the output and operand in overlapping but non-identical registers, i.e. (insn 45 44 66 2 (parallel [ (set (reg/v:TI 5 di [orig:96 i ] [96]) (and:TI (not:TI (reg:TI 39 r11 [orig:83 _2 ] [83])) (reg/v:TI 4 si [orig:100 i ] [100]))) (clobber (reg:CC 17 flags)) ]) "pr106273.c":13:5 562 {*andnti3_doubleword_bmi} where the output is in registers 5 and 6, and the second operand is registers 4 and 5, which then leads to the incorrect split: (insn 113 44 114 2 (parallel [ (set (reg:DI 5 di [orig:96 i ] [96]) (and:DI (not:DI (reg:DI 39 r11 [orig:83 _2 ] [83])) (reg:DI 4 si [orig:100 i ] [100]))) (clobber (reg:CC 17 flags)) ]) "pr106273.c":13:5 566 {*andndi_1} (insn 114 113 66 2 (parallel [ (set (reg:DI 6 bp [ i+8 ]) (and:DI (not:DI (reg:DI 40 r12 [ _2+8 ])) (reg:DI 5 di [ i+8 ]))) (clobber (reg:CC 17 flags)) ]) "pr106273.c":13:5 566 {*andndi_1} [Notice that reg:DI 5 is set in the first instruction, but assumed to have its original value in the second]. My first thought was that this could be fixed by swapping the order of the split instructions (which works in this case), but in the general case, it's impossible to handle (set (reg:TI x) (op (reg:TI x+1) (reg:TI x-1)). Hence for correctness this pattern needs an earlyclobber "=&r", but we can also allow cases where the output is the same as one of the operands (using constraint "0"). The other binary logic operations (AND, IOR, XOR) are unaffected as they constrain the output to match the first operand, but BMI's andn is a three-operand instruction which can lead to the overlapping cases described above. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32} with no new failures. Ok for mainline? 2022-07-15 Roger Sayle gcc/ChangeLog PR target/106273 * config/i386/i386.md (*andn3_doubleword_bmi): Update the constraints to reflect the output is earlyclobber, unless it is the same register (pair) as one of the operands. gcc/testsuite/ChangeLog PR target/106273 * gcc.target/i386/pr106273.c: New test case. Thanks again, and sorry for the inconvenience. Roger diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 3b02d0c..585b2d5 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -10423,10 +10423,10 @@ }) (define_insn_and_split "*andn3_doubleword_bmi" - [(set (match_operand: 0 "register_operand" "=r") + [(set (match_operand: 0 "register_operand" "=&r,r,r") (and: - (not: (match_operand: 1 "register_operand" "r")) - (match_operand: 2 "nonimmediate_operand" "ro"))) + (not: (match_operand: 1 "register_operand" "r,0,r")) + (match_operand: 2 "nonimmediate_operand" "ro,ro,0"))) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI" "#" diff --git a/gcc/testsuite/gcc.target/i386/pr106273.c b/gcc/testsuite/gcc.target/i386/pr106273.c new file mode 100644 index 0000000..8c2fbbb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106273.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-Og -march=cascadelake" } */ +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned long long u64; + +u8 g; + +void +foo (__int128 i, u8 *r) +{ + u16 a = __builtin_sub_overflow_p (0, i * g, 0); + i ^= g & i; + u64 s = (i >> 64) + i; + *r = ((union { u16 a; u8 b[2]; }) a).b[1] + s; +} + +int +main (void) +{ + u8 x; + foo (5, &x); + if (x != 5) + __builtin_abort (); + return 0; +} +/* { dg-final { scan-assembler-not "andn\[ \\t\]+%rdi, %r11, %rdi" } } */