From patchwork Wed Feb 28 05:12:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "See, Chin Liang" X-Patchwork-Id: 878927 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zrkGy4sl0z9s37 for ; Wed, 28 Feb 2018 16:13:13 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B8D5FC22232; Wed, 28 Feb 2018 05:13:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8504DC21F42; Wed, 28 Feb 2018 05:13:05 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7C152C21F42; Wed, 28 Feb 2018 05:13:03 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lists.denx.de (Postfix) with ESMTPS id B459AC21DA6 for ; Wed, 28 Feb 2018 05:13:02 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Feb 2018 21:13:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.47,404,1515484800"; d="scan'208";a="20883788" Received: from pg-nx8.altera.com ([10.104.4.46]) by fmsmga008.fm.intel.com with ESMTP; 27 Feb 2018 21:12:58 -0800 From: chin.liang.see@intel.com To: u-boot@lists.denx.de, Marek Vasut Date: Wed, 28 Feb 2018 13:12:55 +0800 Message-Id: <1519794775-29948-1-git-send-email-chin.liang.see@intel.com> X-Mailer: git-send-email 2.2.2 Cc: Tien Fong Chee , Chin Liang See Subject: [U-Boot] [PATCH] arm: socfpga: gen5: Enabling cache and TLB maintenance broadcast X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Chin Liang See Enabling cache and TLB maintenance broadcast through ACTLR as required by Linux. Signed-off-by: Chin Liang See --- arch/arm/mach-socfpga/misc_gen5.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index a7dcacc..7c7a708 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -239,7 +239,7 @@ static u32 iswgrp_handoff[8]; int arch_early_init_r(void) { - int i; + int i, val; /* * Write magic value into magic register to unlock support for @@ -285,6 +285,15 @@ int arch_early_init_r(void) socfpga_per_reset(SOCFPGA_RESET(NAND), 0); #endif + /* Enable cache and TLB maintainance broadcast as required by Linux */ + /* Read auxiliary control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val)); + val |= (1 << 0); + /* Write auxiliary control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val)); + CP15DSB; + CP15ISB; + return 0; }